Search Results
Wednesday, May 25th, 2016
Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
1 Comment »
Thursday, May 19th, 2016
Tags: Accellera, application, Breker, functional verification, graph, graph-based, JPEG, MPEG, path constraint, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, SystemVerilog, test case generator, testbench, uvm, value constraint
2 Comments »
Wednesday, May 11th, 2016
Tags: Breker, bring-up lab, C/C++, cache coherency, constraints, emulation, ESL, FPGA, functional verification, graph, graph-based, military grade, multi-SoC, portable stimulus, prototyping, rad-hardened, radiation-hardened, realistic use case, scenario model, SoC verification, space, system-on-chip, test case generator, test cases
No Comments »
Thursday, May 5th, 2016
Tags: Accellera, Adapt IP, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, emulation, ESL, FPGA, functional verification, graph, graph-based, IP, multi-SoC, OneSpin, portable stimulus, prototyping, PSWG, realistic use case, Rizzatti, scenario model, simulation, SoC validation, SoC verification, Synopsys, system-on-chip, SystemVerilog, test case generator, test cases
No Comments »
Tuesday, April 26th, 2016
Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, Cavium, constraints, dvcon, DVCon India, EDACafe, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, portable stimulus, prototyping, PSWG, scenario model, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases
No Comments »
Tuesday, April 19th, 2016
Tags: Accellera, assertions, Breker, code coverage, coverage, dvcon, EDA, formal analysis, functional coverage, functional verification, graph, graph-based, IP, portable stimulus, PSWG, reuse, scenario model, SemiconductorEngineering, simulation, SoC verification, system coverage, test generator, uvm
No Comments »
Wednesday, April 13th, 2016
Tags: Bob Smith, Breker, dac, Design Automation Conference, EDA, EDA Consortium, EDAC, embedded systems, ESD Alliance, ESDA, functional verification, graph, graph-based, hardware, IoT, portable stimulus, scenario model, simulation, SoC verification, software
4 Comments »
Tuesday, April 5th, 2016
Tags: Altair, Altera, Apple, Avago, Breker, Broadcom, Cisco, EDA, Freescale, functional verification, Hynix, IHS, Infineon, Intel, Internet of Things, IoT, Leaba, Marvell, MediaTek, mentor, Micron, NVIDIA, NXP, ON, Qualcomm, Renesas, Samsung, SanDisk, semiconductor, Skyworks, SoC, SoC verification, Sony, STMicro, Texas Instruments, TI, Top 20, Toshiba, Western Digital
No Comments »
Wednesday, March 30th, 2016
Tags: Accellera, austin, Breker, cache coherency, cloud, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IoT, NoC, portable stimulus, scenario model, simulation, SoC verification, uvm, VIP
No Comments »
Thursday, March 24th, 2016
Tags: Accellera, Breker, bring-up lab, C/C++, cache coherency, Cadence, constraints, EDACafe, emulation, ESL, FPGA, functional verification, graph, graph-based, mentor, multi-SoC, Peggy Aycinena, portable stimulus, prototyping, PSWG, scenario model, SemiconductorEngineering, SemiWIki, simulation, SoC validation, SoC verification, system-on-chip, SystemVerilog, test case generator, test cases
No Comments »
|
