The Breker Trekker 
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More » Merger Mania and the Still-Changing Semiconductor LandscapeApril 5th, 2016 by Tom Anderson, VP of Marketing
We try to cover a variety of topics here in The Breker Trekker blog, focusing on technical information but mixing in some general industry analysis as well. Two of our most popular posts of all time have involved the annual semiconductor supplier rankings from IHS, Inc. and the large amount of semiconductor industry merger and acquisition (M&A) activity over the last few years. IHS released their 2015 results yesterday, so it’s time for an update on both of these topics. Let’s start by catching up on the M&A front. When we last covered this topic in January, the acquisition of Freescale by NXP and the acquisition of Altera by Intel had both just completed late last year. These closed in time to be reflected in the 2015 supplier rankings. There were several other deals from 2015 that were still pending and, while some of them have now closed, their effects will not be seen until the 2016 results are in. Read the rest of Merger Mania and the Still-Changing Semiconductor Landscape It’s Never too Early to Start Thinking about DACMarch 30th, 2016 by Tom Anderson, VP of Marketing
For those of us who have been in the EDA business on one side or the other (or both), the Design Automation Conference (DAC) is one of the highlights of every year. I almost hate to admit it, but this year holds DAC number 29 for me. I’ve been to San Francisco, San Diego, Los Angeles, Anaheim, Las Vegas, Dallas, New Orleans, and Orlando, most of them multiple times. But one of the most fun locations was Austin, where DAC was held for the first time three years ago, and where we will return in just a few short months. There will be plenty of time later for us to fill you in on what Breker will be doing at DAC this year. Since the program for the 53rd annual conference just went live, I thought I’d share some initial impressions and predict some likely highlights. Of course as an exhibitor I’m already deep in planning for the show, but I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show. Read the rest of It’s Never too Early to Start Thinking about DAC A Portable Stimulus Standard Will Take Time, but the Technology is Here TodayMarch 24th, 2016 by Tom Anderson, VP of Marketing
Last week, we used an update on the Accellera Portable Stimulus Working Group (PSWG) presented at the Design and Verification Conference and Exhibition (DVCon) as a jumping-off point to discuss the status of this standardization effort and some key aspects of the three proposals currently under consideration. We were not the only blog to cover portable stimulus topics from DVCon; Brian Bailey of SemiconductorEngineering and Bernard Murphy from SemiWiki also posted their observations. Earlier this week, EDACafe blogger colleague Peggy Aycinena posted a thought-provoking look at PSWG and the portable stimulus challenge. In regards to the scope of the proposed standard, she noted “a distinct wow factor in all of this, it’s so comprehensive” and said “this whole effort seems massive to me.” Today we’d like to respond to Peggy’s comments and questions, noting both the challenges of a portable stimulus standard and the availability of a working solution today. Read the rest of A Portable Stimulus Standard Will Take Time, but the Technology is Here Today A Snapshot Update on the Accellera Portable Stimulus EffortMarch 16th, 2016 by Tom Anderson, VP of Marketing
As all of our regular readers are aware, the software-driven SoC verification space pioneered by Breker is becoming more of a mainstream approach every day. One good barometer for the industry shift now underway is the standardization effort in progress within the Accellera Portable Stimulus Working Group (PSWG). The amount of interest in this standard has skyrocketed recently, and portable stimulus was a hot topic at the Design and Verification Conference and Exhibition (DVCon) two weeks ago. As we promised when we first began discussing the PSWG, we don’t believe in sharing internal details of standardization work in a public blog. However, the group was offered a slot to present an update at an Accellera-sponsored lunch during DVCon. So the PSWG put together a set of slides with information to share publicly and Vice-Chair Tom Fitzpatrick of Mentor did a nice job of presenting them. For those of you who could not attend, we’ll summarize the current status in today’s blog post. Read the rest of A Snapshot Update on the Accellera Portable Stimulus Effort DVCon Panel: Trying to Define the ESL ShapeshifterMarch 9th, 2016 by Tom Anderson, VP of Marketing
In last week’s post on The Breker Trekker we summarized activities at the Design and Verification Conference and Exhibition (DVCon) in San Jose, including a brief mention of the “Redefining ESL” panel on Wednesday morning. I attended this session and took detailed notes in anticipation of blogging about it, but in the process gave some thought to my own opinions about the electronic system-level (ESL) domain and how they intersect with those of the panel participants. The panel was organized by Dave Kelf of OneSpin Solutions and PR guru Nanette Collins, and moderated by Brian Bailey of SemiconductorEngineering. Brian is a long-time observer of the ESL market so I expected him to ask some tough questions. He opened by remarking that the term is generally credited to the late EDA analyst Gary Smith. Many of us who knew Gary sometimes teased him a bit on his regular pronouncements that “this will be the year of ESL.” Read the rest of DVCon Panel: Trying to Define the ESL Shapeshifter Portable Stimulus Was Front and Center at this Year’s DVConMarch 3rd, 2016 by Tom Anderson, VP of Marketing
We’ve just returned from our most important trade show of the year: the Design and Verification Conference and Exhibition (DVCon) in San Jose. Sure, DAC is a bigger show, but it covers all of EDA and so lacks the front-end digital focus of DVCon. We previewed the event over our last few blog posts and today we’d like to summarize what happened and make a prediction or two about how this particular DVCon will affect the industry. The biggest news for us was that portable stimulus seemed to be on everyone’s lips this year. Many of the engineers who stopped by to visit our booth had heard the term and were aware that the Accellera Portable Stimulus Working Group (PSWG) is developing a standard. If they didn’t know what portable stimulus was, they almost surely knew by the end of the show. Read the rest of Portable Stimulus Was Front and Center at this Year’s DVCon Automatically Generating Interacting, Self-Checking Test Cases for 144 CPU CoresFebruary 24th, 2016 by Tom Anderson, VP of Marketing
We hope that the title of this blog post piqued your interest, because we don’t believe that we’ve seen anyone anywhere claiming to do automated multi-SoC verification at this level. Two weeks ago, we previewed next week’s Design and Verification Conference and Exhibition (DVCon) in San Jose. We highlighted one particular talk being co-presented by Breker and Cavium on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session on Tuesday, March 1. We teased you with the statement that this talk will describe “generating test cases for a multi-SoC configuration with well over 100 cores” and it’s time to tell you a bit more now that we have issued a press release on our project with Cavium. Of course, we need to reserve some of the details for the paper in the DVCon proceedings and the talk itself so that new material is being presented at the conference. We heartily encourage you at attend the show and hear for yourself. Read the rest of Automatically Generating Interacting, Self-Checking Test Cases for 144 CPU Cores Why Is Cache Coherency So Hard to Verify?February 19th, 2016 by Tom Anderson, VP of Marketing
In last week’s post, we provided a preview of the program at the annual Design and Verification Conference and Exhibition (DVCon) in San Jose, coming up in ten days. We mentioned some of the interesting talks and other activities there, and focused in particular on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” on Tuesday morning. The paper for this session was co-authored by Breker and Cavium, and both companies will present together at DVCon. The paper and presentation describe the use of our Cache Coherency TrekApp and TrekSoC-Si to automatically generate self-checking, portable test cases for more than 100 CPU cores in a multi-SoC configuration in the Cavium bring-up lab. To set the stage for this story, today we’d like to revisit some of the reasons why cache coherency is so hard to verify and why an automated approach is the best solution. A Preview of the Upcoming DVCon in San JoseFebruary 10th, 2016 by Tom Anderson, VP of Marketing
Regular readers of The Breker Trekker know that we like to preview, review, and dissect technical conferences and trade shows that are of interest to verification engineers. Perhaps the conference we’ve covered the most has been the annual Design and Verification Conference and Exhibition (DVCon) in San Jose. As far as we know, this is the biggest event anywhere focused on digital and system design and verification, a nice complement to the analog-ish DesignCon. As a matter of fact, DVCon has become so successful that there are now regional conferences in India and Europe in addition to the U.S. show. We’ve strongly supported DVCon India, including serving for all three years on the Promotions Committee, and have participated in DVCon Europe as well. But those are a bit in the future; DVCon (U.S.) 2016 is coming up in a just a few weeks. The program is online now, so we thought we’d review it and suggest some sessions of possible interest. Read the rest of A Preview of the Upcoming DVCon in San Jose Expanding Our Scope to Multi-SoC System VerificationFebruary 3rd, 2016 by Tom Anderson, VP of Marketing
For more than four years now, Breker has branded itself as “The SoC Verification Company” and many people acknowledge our expertise in this domain. As we have discussed before on The Breker Trekker, our initial products focused on generating purely transactional tests for a simulation testbench, usually compliant with the Accellera Universal Verification Methodology (UVM) standard. When we extended our products to generate C code that runs on the embedded processors found within SoCs, we delivered on our “tagline” promise. Since our early focus on simulating an SoC, we have expanded our technology and our product line to generate C test cases that run on embedded processors in emulation, FPGA prototypes, and actual silicon in the bring-up lab. In talking about what we do, we struggle to choose between “SoC” and “system” since for many of our customers the terms are synonymous. But we also have users verifying multi-SoC systems, and today we’d like to address that topic. Read the rest of Expanding Our Scope to Multi-SoC System Verification |
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