Archive for the ‘Uncategorized’ Category
Wednesday, December 16th, 2015
Do you want to hear all the behind-the-scenes dirt from a workshop on the future of the MTV cable channel? Well, you’ll have to look elsewhere. “MTV” in this case means the International Workshop on Microprocessor Test and Verification, which celebrated its 16th incarnation in Austin two weeks ago. Although the name of the workshop has officially expanded to “Microprocessor and SOC Test and Verification” rest assured that the delightfully ambiguous abbreviation “MTV” will remain.
This was only my second time at this event, but I wish that I had been able to attend more. The setting is the top floor of the Hyatt Regency, with great views of Lady Bird Lake (formerly Town Lake) and downtown Austin. However, I noticed that recent high-rise construction has now blocked the sight of the Texas State Capitol from the hotel. The view might be distracting if not for the fact that the technical committee put together an interesting and diverse program, including a panel on portable stimulus.
(more…)
Tags: Accellera, ARM, austin, Breker, Cadence, EDA, emulation, FPGA, Freescale, functional verification, graph, graph-based, horizontal reuse, mentor, MTV, node, portable stimulus, PSWG, scenario model, silicon, simulation, SoC verification, Synopsys, test generator, vertical reuse
No Comments »
Thursday, December 10th, 2015
The past two weeks, we’ve been having a bit of fun playing alchemist and letting readers in on some of the deep, dark secrets of graph-based verification technology. This week, we conclude the series by showing some additional capabilities for our scenario models that are easy to control and view in a graph visualization. Our point is, of course, that graphs are a natural way to represent data flow and verification intent with no advanced degrees from MIT, IIT, or Hogwarts required.
As a quick reminder, graph-based scenario models begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. Breker’s Trek family can traverse the graph from left to right, randomizing selections to automatically generate test cases tailored to run in any target platform. Today, we continue using our example of a scenario model to verify that an automobile can move forward or stop.
(more…)
Tags: Accellera, Breker, constraints, cross-coverage, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, system-level coverage, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Thursday, December 3rd, 2015
Last week, we began exploring some of the ancient, mysterious powers of graph-based scenario models to show their power for verification and ability to capture the verification space, many aspects of the verification plan, and critical coverage metrics. We’re just kidding about the first part; there’s nothing at all mystical or magical about graphs. In fact, this series of posts is intended to show the opposite and demonstrate with a easy-to-follow example the value of graphs.
As we noted in our last post, graph-based scenario models are simple in concept: they begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. An automated tool such as Breker’s Trek family can traverse the graph from left to right, randomizing selections to generate test cases that can run in any target platform.
(more…)
Tags: Accellera, Breker, constraints, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Tuesday, November 24th, 2015
If there’s one thing that Breker is known for, it’s the use of graphs for verification. From our earliest days, we harnessed the abstraction and expressive power of graph-based scenario models to capture the verification space, many aspects of the verification plan, and critical coverage metrics. As we reported in a post a few weeks ago, it looks certain that the industry will follow our lead and base the upcoming standard from Accellera‘s Portable Stimulus Working Group (PSWG) on a graph representation.
As discussions have proceeded both within the PSWG and informally with interested parties, it has become clear that “graph” may not mean the same thing to all people. Our view of graphs is precisely defined in a way that makes it easy for users to create them and feasible for our tools to generated complex, multiprocessor test cases from them. Most of the key concepts can be communicated easily by the use of a familiar example, which we will begin in today’s post and continue next week.
(more…)
Tags: Accellera, Breker, EDA, functional verification, goal, graph, graph-based, horizontal reuse, node, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Tuesday, November 17th, 2015
In last week’s post, we dissected the results for verification languages and methodologies from a recent survey by Mentor Graphics and Wilson Research Group. The main result was that SystemVerilog is growing in popularity on all fronts, but we observed that C/C++ has a significant presence. We also argued that the survey’s focus on simulation likely resulted in C/C++ being under-represented since these languages are widely used for verification with hardware platforms and for silicon validation in the lab.
We see C/C++ as the common link for many types of programming activities, and so widely known that many consider it the lingua franca of software. Just type “lingua franca C/C++” into your favorite search engine and scan the results for some interesting arguments and a few counter-arguments. To be fair, some observers consider C the lingua franca and downplay C++. We tend to group them together since object-oriented programming is now widespread and so moving from C to C++ should be a natural transition.
(more…)
Tags: Accellera, API, Breker, C/C++, EDA, ESL, functional verification, horizontal reuse, Java, Mentor Graphics, portable stimulus, PSWG, Python, Ruby, simulation, SoC verification, subsystem, SystemVerilog, uvm, vertical reuse, VHDL
No Comments »
Wednesday, November 11th, 2015
One of the cliches we hear from time to time in the industry is “designers want to stick with a single language, but verification engineers love learning new things.” The implication seems to be that because verification engineers have diverse jobs that require them to juggle lots of different tools and models, they necessarily have to learn new languages and methodologies on a regular basis. Of course, they may not actually love learning new languages; doing so may just be in the nature of their work.
Regardless of whether or not they “love” new languages, it is clear that most verification projects involve multiple languages and multiple approaches. One way to gauge the current situation is to turn to the excellent survey that Mentor Graphics performs with Wilson Research Group every couple of years. Harry Foster wrote a series of posts on the Mentor verification blog that give considerable insight into what verification (and design) engineers are doing on real projects.
(more…)
Tags: Accellera, API, Breker, C/C++, Cadence, e, EDA, ESL, functional verification, Harry Foster, horizontal reuse, Mentor Graphics, OVL, portable stimulus, PSWG, simulation, SoC verification, subsystem, Synopsys, SystemC, SystemVerilog, Universal Verification Methodology, uvm, vertical reuse, VHDL
1 Comment »
Tuesday, November 3rd, 2015
The long-established trade association EDA Consortium (EDAC) has started several new initiatives to extend its membership to IP suppliers and to offer more value to its members through new programs. New EDAC Director Bob Smith has a bunch of innovative ideas and I have little doubt that they will breathe new life into the organization. I had the pleasure of working with Bob when he did some consulting for Breker several years ago, and he’s a true professional.
Last week I attended the first in a series of legal-themed events sponsored by EDAC. I expected that the title “Patents and Patent Litigation: Develop, Strengthen, and Protect Your Intellectual Property” would draw well, and indeed the conference room at SEMI Global Headquarters in San Jose was packed. I won’t attempt to cover the wide range of topics addressed, but I would like to hit a few highlights from the panel discussion and the excellent questions from the moderator and the audience.
(more…)
Tags: Accellera, Breker, Cadence, EDA, EDAC, Liccardo, mentor, patents, San Jose, standards, Synopsys, Trek, TrekApp, TrekSoC, USPTO
1 Comment »
Wednesday, October 28th, 2015
Those of us of a certain age will remember the secret decoder rings promoted by various products and TV shows. They generally used a simple substitution code to map letters to numbers. According to Wikipedia these have been offered as recently as 2000, so perhaps they are known to younger readers as well. What’s germane to today’s blog post is that formal services company Oski Technology has cleverly used this device as a graphical element in promoting its “Decoding Formal” Club series.
I’ve reported before from these events, which I believe have been very effective at advocating for formal analysis, sharing tricks and techniques, and demystifying what was once regarded as an arcane academic approach to verification. Last week I attended another Decoding Formal Club forum and, as usual, was impressed by the depth of the presentations. Since formal is always a popular topic among readers of The Breker Trekker, I’m going to share a few highlights from that afternoon.
(more…)
Tags: Accellera, ARM, assertions, Breker, Broadcom, cache coherency, constraints, EDA, formal, functional verification, graph-based verification, NVIDIA, oski, portable stimulus, properties, scenario model, SoC verification, standards, Trek, TrekApp, TrekSoC
1 Comment »
Thursday, October 22nd, 2015
One of the most interesting events I attended last year was the 2014 Silicon Valley IP Users Conference, organized and presented by IPextreme and their Constellations program partners. It was a wonderfully well-organized day, with excellent speakers in the fun environment of San Jose’s Winchester Mystery House. On Tuesday of this week, I attended the 2015 version of the conference and once again was impressed by both the technical content and the networking opportunities.
This year we were nestled in the foothills of Los Gatos at the historic Testarossa Winery, coincidentally on the same day that Manresa Restaurant just down the street was awarded its third Michelin star. With a wine tasting after the presentations, we were all in a celebratory mood. I was most intrigued by the panels, so I’d like to devote today’s post to a summary of some of the more interesting points I heard and what they might mean for the semiconductor industry, the EDA industry, and Breker.
(more…)
Tags: Accellera, Breker, DV, ESL, functional verification, IoT, IP, IPextreme, portable stimulus, SoC, SoC verification, uvm, VIP
No Comments »
Friday, October 16th, 2015
We’re coming up to the two-and-a-half-year anniversary for The Breker Trekker, with 124 published posts. Initially I promised a post every other week, but after looking at the viewing patterns I quickly realized that I had to publish every week to establish a consistent audience. There’s always something to talk about in this fast-paced world, whether something new at Breker, standards activity, observations about the EDA industry, or analysis of the customers who drive our business.
Today I’d to acknowledge a second Breker blog that has actually been around longer than this one. Just over three years ago, Breker board of directors member Michel Courtoy started a series of posts in Electronic Engineering Times to offer advice to startups. He has published 28 such posts, and has covered an amazing amount of territory. I suppose that I should have done some “cross-promotion” earlier, but at this point I would like to highlight some of Michel’s sage advice. (more…)
Tags: Breker, EDA, EE Times, Electronic Engineering Times, functional verification, graph, graph-based, Michel Courtoy, portable stimulus, realistic use case, scenario model, simulation, SoC verification, software, software-driven verification, startups, test generator
No Comments »
|
