It seems like ancient history now, but in the not so distant past, verification was performed by one tool – simulation;  at one point in the flow – completion of RTL;  using one language and methodology – SystemVerilog and UVM. That changed when designs continued to get larger and simulators stopped getting fast enough.  Additional help became necessary in the form of emulators and formal verification, but that coincided with an increasingly difficult task of creating a stable testbench. It was no longer possible to migrate a design from a simulator to an emulator without doing a considerable amount of work on the testbench. (more…)