A Further Preview of DVCon India 2016

Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.

As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges

Sushil Gupta, a Group Director of Engineering in the Verification Group at Synopsys, will present “Today’s SoC Verification Challenges: Mobile and Beyond” with a focus on how the end markets such as mobile and the Internet of Things (IoT) place increasing demands on chip development teams. He also will offer some predictions for the future. Since he joined Synopsys with its acquisition of Atrenta and has worked at several other EDA companies, we anticipate a broad perspective.

Academia is more active in this year’s show, including an invited keynote from Kamakoti Veezhinathan, Senior Professor in the CSE Department at IIT Madras. He will discuss the major “Make in India” initiative being driven by the Indian government and focus specifically on a secure computation and communication framework being developed in his research group. Security and safety are themes that appear everywhere in this year’s DVCon program, so this talk should be very timely.

As we mentioned before, the program is divided into two tracks: electronic system level (ESL) and design and verification (DV). The keynote for the ESL track will be presented by Canon’s Senior Director and Head of India Systems Development Center, Subrangshu Das. With the title “Microprocessors to Smartphones to Autonomous Cars to Deep Learning” we can surely expect an application-centric talk on how new product domains will drive new requirements for ESL flows.

The DV keynote, “Verification for Complex SOCs,” will be presented by Alok Jain, a Senior Group Director in the Advanced Verification business unit at Cadence. He is a well-known expert in formal verification, but his talk will also address such critical topics as testbench development, simulation speed, verification reuse from pre-silicon to post-silicon platforms, merging coverage metrics from all platforms, and effective debug on all platforms. That’s a lot to cover!

Each track also has a panel of industry luminaries tackling a hot topic. The ESL panel “An Entry Level Vehicle for IoT Market Space” will ponder how ESL can foster rapid prototyping and early exploration for IoT designs. The panel participants are from Infineon, Intel, NXP and Synopsys. On the DV side, emulation expert Lauro Rizzatti will moderate a discussion on “The Future Verification Flow” with panelists from Broadcom, Qualcomm, and Test and Verification Solutions (TVS).

Finally, the tutorials and presentations that we discussed last time will be complemented by 14 posters. The authors will be available to answer questions during breaks in the technical program on the second day. Many of these look interesting; a few titles that stand out for us are:

• Pre-Silicon Power Management Verification of Complex SOCs: Experiences with Intel Moorefield (Intel)
• Virtual Platform for Architecture Exploration and Performance Analysis of Memory Sub-System (HCL)
• Methodology to Combine Formal and Fault Simulator to Measure Safety Metrics (Infineon)
• Implementation of Ruby Language Binding to UVM (AMD)

Congratulations to the DVCon India Technical Program Committee for pulling together such an interesting program. There should be topics of interest to just about anyone involved in design or verification. When you attend, please don’t forget to stop by the Breker booth at the vendor exhibition and say hello. We will see you in Bangalore!

Tom Anderson

The truth is out there … sometimes it’s in a blog.

Tags: acceleration, Accellera, Breker, Broadcom, Cadence, coverage, debug, dvcon, DVCon India, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, Infineon, Intel, mentor, multi-SoC, multi-threaded, multiprocessor, NXP, portable stimulus, PSWG, Qualcomm, reuse, scenario model, simulation, SoC verification, software-driven verification, Synopsys, test generator, transactional, TVS, Universal Verification Methodology, UVC, uvm, VIP

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