IEEE Reports that C is the Most Popular Programming Language

As some of you may have seen, two years ago the IEEE created an app that ranks the popularity of dozens of programming languages. They use twelve different metrics, from search results and social media mentions to technical publications and requirements listed in job openings. If you don’t like the way  that they use these metrics, you can create your own ranking using your own mix. It’s really quite a clever idea and it generates lots of discussion every year.

For 2014 and 2015, C held the #2 spot, just below Java in the rankings. The big news this year is that C has edged into first place, although the top two spots remain very close as measured by the metrics the IEEE has chosen to use. C++ was in the #3 spot for the past two years, but for 2016 flipped places with Python. As you all know, we are strong advocates of C/C++ for verification and so we’d like to share some thoughts on these results and what they mean for our industry.

Let’s start by pointing out that the IEEE survey covers a very broad usage of programming languages. They define the general categories of Web, mobile, enterprise, and embedded; we’re not certain where application of programming languages for functional verification even fits in this list. However, we’ve included the top 40 languages for this year along with the results from 2014 and 2015 in the following table, and since Verilog and VHDL show up we can be sure that EDA users are represented somehow:

Given the high placing of C/C++, it seems likely that these languages play a significant role in all the categories covered by this survey, including EDA and chip verification. This is corroborated by survey results reported last year by Mentor Graphics and Wilson Research Group that included which languages and methodologies were used for verification. SystemVerilog and the Universal Verification Methodology (UVM) dominated, but about a third of all testbenches also contained C/C++ code.

We analyzed these results in a blog post last fall, pointing out that C/C++ usage was very likely under-represented due to the focus on simulation and testbenches. For verification and validation platforms beyond simulation, there is no SystemVerilog (or Verilog, VHDL, SystemC, or e) in the mix. There may be some Python and Perl in use, but the majority of embedded code run in in-circuit emulation (ICE), FPGA prototypes, and silicon in the bring-up lab is almost certainly written in C/C++.

As we argued in a follow-up post, we see C/C++ as the lingua franca for verification and validation. As shown by the surveys we’ve just discussed, these languages are very widely known and very widely used. It is easy to find both fresh university graduates and experienced engineers who know C very well. Many also know C++ and those who don’t can pick it up easily since they already know the basics of object-oriented programming from other languages such as Java and Python.

This discussion is highly relevant in the context of portable stimulus and the standard under development within Accellera. We have maintained that this standard must use C/C++ as a form of input specification because its usage and users span all verification platforms. We have shown how all the layers required for a portable stimulus solution can be specified in standard C/C++ with no new constructs added to the language. It’s nice to see the latest IEEE survey re-asserting the popularity of C and its derivatives.

Finally, we have to note how amazing it is that C usage is still growing. The language was developed at Bell Labs more than 40 years ago and, while it has been extended and standardized, early users would still instantly recognize it. As with Unix, also developed at Bell Labs and also being used in more ways every day, solid technology designed with the user in mind can last a long time. Now that sounds like a good subject for a future blog post.

Tom A.

The truth is out there … sometimes it’s in a blog.

Tags: acceleration, Accellera, API, Breker, C/C++, EDA, emulation, FPGA prototyping, functional verification, graph, graph-based, horizontal reuse, IEEE, Java, Mentor Graphics, multi-SoC, multiprocessor, Perl, portable stimulus, programming languages, PSWG, Python, reuse, scenario model, simulation, SoC verification, software-driven verification, subsystem, SystemVerilog, test generator, testbench, Universal Verification Methodology, uvm, vertical reuse, VHDL

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