Archive for October, 2014
Thursday, October 30th, 2014
In last week’s post, we discussed in detail how Breker’s TrekSoC and TrekSoC-Si products can verify the performance of your SoC by stressing every aspect of its functionality. Shortly before that, we announced a partnership with Carbon Design Systems to complement their fast, accurate processor models with TrekSoC. About two months ago, we introduced the new Coherency TrekApp and described how it can verify multi-processor cache coherency with minimal effort.
You can see a strong theme here: multi-processor SoC designs, fast simulation models, automatic generation of multi-threaded, multi-processor test cases, and test cases powerful enough to gather realistic performance metrics from pre-silicon simulation. But what if you don’t have multiple processors or caches in your SoC design? There’s a clear sense emerging in the industry that more and more chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. Let’s explore this topic more in this post.
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Tags: Breker, cache, Carbon, coherency, CPAK, DV, functional verification, IoT, IP, portable stimulus, SoC, SoC verification, TrekApp, TrekSoC, TrekSoC-Si, uvm, VIP
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Wednesday, October 22nd, 2014
For those unfamiliar with the expression in the title, bringing someone (or something) to its knees means making it submissive. It’s a metaphor possibly derived from the act of hitting someone so hard that his knees buckle and he falls to a kneeling position. Why such a nasty term to start this post? Because when you want to verify the performance of your SoC you want to stress every aspect of it. You want to be mean to it. You want to bring it to its knees.
The most common way to do this is to run production software (operating systems plus applications) on a virtual prototype, a high-level system model created by architects before RTL implementation begins. This is not easy; it takes effort to set up workloads that will stress the design and often production software is not ready at this early stage of the SoC project. Further, this verifies only the high-level model, but RTL simulates too slowly to replicate the same tests, or often to boot the operating system at all.
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Tags: acceleration, applications, apps, Breker, coverage, EDA, emulation, FPGA prototyping, functional verification, graph, performance, portable stimulus, reuse, scenario model, SoC verification, transactional, TrekSoC, TrekSoC-Si, TrekUVM, UVC, uvm
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Thursday, October 16th, 2014
I spent Tuesday of this week in the Winchester Mystery House, San Jose’s best-known tourist attraction, hearing a wide variety of opinions about design IP, verification IP (VIP), the Internet of Things (IoT), and related topics. “Unlock the Mystery of IP: Silicon Valley IP Users Conference” was organized and presented by IPextreme and their Constellations program partners. I found most of the talks quite interesting, and would like to share some thoughts on what the experts’ projections might mean for Breker and our customers.
There is no doubt that the increasing use of IP is key to designing ever larger chips. Kands Manickam of IPextreme noted that, over the next five years, the compound annual growth rate (CAGR) of IP blocks and subsystems is expected to be 12% versus 3.5% for semiconductors. Randy Smith of Sonics reported that the average large chip today has about 120 blocks, growing to more than 200 by 2018. We already know that VIP reuse is not as effective as design IP reuse, and these projections will only exacerbate the gap.
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Tags: Accellera, Breker, DV, ESL, functional verification, IoT, IP, IPextreme, portable stimulus, SoC, SoC verification, uvm, VIP
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Wednesday, October 8th, 2014
Last week we summarized some of the activities at the inaugural DVCon India. Breker was not the only company impressed by this show. For example, CVC wrote two posts on their VerifNews blog describing the excitement and range of technical content at the show. Gaurav Jalan captured several aspects of the show in his Sid’dha-karana blog, focusing specifically on the keynote speakers. The Agnisys blog also provided a nice overview. Clearly this was a very successful event.
The high quality of the technical content and the excellent attendance at DVCon lead me to think about how much India has changed in just a few years. I first had an engineering team there in 1995, nearly 20 years ago. I recall my first trip to India very well and the contrast with recent visits is tremendous. I’ve been deeply impressed by the evolution of electronics development in India and I see the DVCon success as both a tribute to where the community is today and a sign of even better things to come.
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Tags: Accellera, Bangalore, Breker, chennai, DV, dvcon, ESL, functional verification, India, madras, portable stimulus, SoC, SoC verification, uvm
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Friday, October 3rd, 2014
Over the last several blogs posts, we’ve twice previewed the very first DVCon India show, celebrating it as a sign of India’s ever-growing importance in the electronics industry. We also mentioned that our co-founder and CEO Adnan Hamid would be presenting in two tutorials and helping to staff our booth in the exhibition. Now that the event is over and Adnan has returned from his travels, we’d like to fill you in what turned out to be a great event.
We have heard nothing but positive comments from attendees, vendors, and organizers. The conference was well attended, full of strong technical content, and well run. Perhaps the dominant theme to emerge was the importance of the “portable stimulus” effort undertaken by Accellera and the solutions available to meet some or all of the vision. It may be a stretch to call DVCon India the “Portable Stimulus Conference” but surely the first day (Thursday) was “Portable Stimulus Day” and we’ll explain why.
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Tags: Accellera, Bangalore, Breker, Cadence, CVC, DV, dvcon, ESL, functional verification, India, mentor, portable stimulus, Synopsys, uvm
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