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Archive for December, 2016

Flex Logic & TSMC: embedded FPGA cores on 16nm FinFETs

Wednesday, December 14th, 2016

 


Flex Logic announced some astonishing news this week
– the completed design of a “high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions.”

In a phone call to discuss the announcement, Flex Logic CEO and Co-founder Geoff Tate was clearly ebullient: “Last August we were talking about TSMC’s 40-nanometer ULP, ultra low power, and now this week we’re talking about the first 16-nanometer finFET plus.

“This one, our EFLX 100, is like the one we announced at 40 nanometers – but at 16 nanometers it will run much faster!

“We’ve done extensive measurements [to confirm] for many applications that these cores will run at 1GHz or faster, even in worst-case temperature conditions.”

(more…)

IP Design Challenge: efabless & X-FAB promote Ingenuity, February deadline

Wednesday, December 7th, 2016

 


If you’re a designer looking for a rare opportunity to shine, look no further
. The folks at Erfurt-based X-FAB and Silicon Valley-based efabless hope to “further ingenuity” by extending a challenge to anyone in the world willing to accept it.

What they’re looking for are IP designs applicable to an ultra-low power voltage reference, and the companies are willing to make it worth your while.

If your design is one of the top three selected, you’ll receive a monetary award and your IP will be made available to a global customer base through both X-FAB’s IP web portal and efabless’ online marketplace.

Best of all – you’ll hold onto all rights for your submission.

(more…)




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