Hi, I’m Robert Jones, the DAC 2010 Tutorials Chair.The executive and tutorials committees have been working for almost a year on this summer’s tutorial program.I’m excited about the topics; I hope that you will find them as compelling as I do.The speakers are all domain experts; the speaker lists read like a “Who’s Who” in the respective areas.

This year, we will offer seven tutorials; four full-day, two half-day, and one for two hours.The topics are timely and relevant: ESL design and prototyping, low power, SystemC for multiple domains, analog circuit design, and 3D ICs.Two of the tutorials cover topics outside of EDA technology: marketing and software development.Each tutorial will follow the DAC tradition of providing clear, informative education from domain experts.

Monday offers two full-day tutorials. The first, ESL Design and Virtual Prototyping of MPSOCs, will provide a comprehensive introduction to the fast-growing world of Electronic System Level (abstract) design. Attendees will learn about current ESL design techniques, future trends, and participate in exercises via a live CD distributed to all participants.

The second Monday tutorial, Low Power from A to Z, covers one of today’s hottest (pun intended) issues in design and design automation. This tutorial will provide a comprehensive overview of low-power approaches at all levels of the design process, from process technology to system architecture.

Two tutorials will cover important topics for EDA professionals that are not usually part of a standard Electrical Engineering curriculum. On Monday morning, the two-hour tutorial Marketing of Technology – The Last Critical Step will teach a technically-trained professional about go-to-market strategies and planning.

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While many of us are just getting used to writing “2010” on our documents and personal checks, it’s clear that the economic impact of 2009 will not be forgotten any time soon.
The consensus across diverse constituencies – ranging from world leaders to industry heads and many leading economists – is clear. We are not simply recovering from a cyclical recession; we are entering into a Global Economic Reset. While this Reset creates challenges for balancing our labor forces and manufacturing capacity, it provides a real opportunity for electronic design automation (EDA) providers to demonstrate the intrinsic value of our technologies.

The semiconductor industry stands on the shoulders of its EDA tool providers and we must deliver the innovations and productivity necessary to feed and nurture the designers that have come to rely on us. It is only through this combination of innovation and productivity that we can provide the sustained value that will serve as the growth catalyst our broader ecosystem thrives on.

Innovation without context is irrelevant, however, so it’s essential that we deliver technology and capability in a manner that can be applied and exploited by the intended user. Through our interactions and discussions with designers, we consistently hear that many EDA design tools have exceeded the core requirements for a majority of the user base. In fact, just last week one of our customers referred to their usage of a “big three” vendor tool as “firing up the space shuttle to go to the corner store for milk.” This excess is understandable, as the market leaders are driven by the most extreme requirements for their (niche) user base working in the smallest geometries with unique needs. What’s tragic is that these cumbersome, overburdened tool flows have become the acceptable paradigm for the entire industry. The result is an ever-increasing gap between the requirements of most users and the features and functionality provided by the market-leading tools.

We believe 2010 is ripe for a new paradigm – one where “less is more.” An approach to tool design that delivers just the right mix of top-notch features and functionality that is squarely aligned with requirements. This concept of elegant, efficient design is what John Tanner embraced when he founded Tanner EDA twenty-two years ago and it’s an approach that we believe is not only relevant — but imperative — today.

Delivering on “less is more” is difficult. Anyone who has tried to distill a presentation to one slide or simplify a complex design knows that it requires more than just skill. One must achieve a deep level of understanding in order to get to the essence of the topic or issue. For EDA products, we think that functionality will not include superfluous features but instead will deliver excellent, tested and well supported solutions. This cannot be achieved in a vacuum; it requires the leveraging of users, partners, and even competitors. We believe this leverage – achieved through models such as “open innovation” (originally coined by Professor Henry Chesbrough) — is essential to achieving and sustaining “less is more.”

The open innovation business model offers a compelling framework for consideration in the EDA industry. With a core principle that ideas and intellectual capital can come from outside the traditional boundaries and connections, open innovation can bring new capabilities and technologies efficiently and effectively. Companies in the broader EDA ecosystem (such as Qualcomm) have already embraced open innovation as a means of effectively bolstering their innovation capacity and effectiveness.

While perhaps not considered a traditional example of open innovation, process design kits (PDKs) offer a congruent model for connecting technologies and intellectual property (IP) from one domain (IC fabrication) to another (design). One perspective on PDKs is that they are simply rule-sets that provide all users with a consistent base of information; effectively eroding opportunity for differentiation within a design. However, further consideration reveals that there are several other dimensions to PDKs where unique IP can be inserted for sustained differentiation.

One such dimension is PDK selection: simply identifying and applying technologies within and across foundries. A working example of this is Tanner’s recent collaboration with Sound Design Technologies (SDT). SDT and Tanner are launching a PDK to allow users to include advanced integrated passives technologies and 3D chip packaging capabilities in their designs. This offers the potential for substantial space savings as well as production and operating cost reductions. The other dimension here is access – where a tool vendor’s use of standard programming languages and opening of PDKs can provide a designer with the access and opportunity to customize and create differentiation.

Productivity is not exclusive from innovation; in fact, we believe that in this new era of doing more with less, designers will require more productivity from their EDA tools if they are to achieve the breakthroughs demanded by their customers. We believe that 2010 will see productivity requirements expand beyond the basics of performance, security and capability. Significant advances in the area of design environments and analog automation will achieve prominence. And designers will be able to use more efficient, focused tools to deliver profound breakthroughs for business and society.

Is there a disconnect in your die, package and board design methodology? As technologies evolve to meet demands of higher performance, smaller size and lower cost, there are several challenges in the design of chips, packages and boards which must be addressed with an integrated analysis and verification methodology.

For example, maintaining power integrity means ensuring that the entire power delivery from the voltage regulator on the PCB to the transistor on the die meets the device power supply requirement. This involves designing and optimizing the location of the voltage regulator, PCB and package de-coupling capacitors, power plane impedance, bump placement, on-die power grid, on-die de-coupling capacitors and switching transients in one design and analysis environment. Sufficient data sharing needs to happen between each of the design teams to ensure that the final working part delivers the supply current as needed by the chip within the specified voltage fluctuation limit.

On the other hand, high-speed memory and serial interfaces have very stringent requirements for simultaneous switching noise resulting from their need to maintain the fidelity of the transmitted and received signals. The simultaneous consideration of the IO ring design, IO and decoupling capacitor cell placement, input switching pattern, and package/board power and signal layouts is necessary to meet the goals of near end and far end SSN.

However, as these challenges become increasingly critical to the success of next generation of designs and systems, there is a singular lack of tools and methodologies to address these issues. Multiple disparate techniques exist with contention about the efficacy of each. Tool-sets exist but address only parts of the problem. For example, frequency domain analysis tools employing fast electromagnetic field solvers have looked at the mid and low frequency power delivery network system noise. Hence, time domain analysis tools are needed to solve for the high frequency noise that result from the switching of devices on the chip. But these time domain analysis tools need accurate models of the package and board to provide realistic on-die voltage and current waveform data. Similarly for IO signal integrity analysis, most analysis methods compromise either on the modeling sophistication or on data inclusiveness to generate results in a reasonable time-frame. For example, either the entire IO bank is not considered in the simulation or the signal/power ground network coupling are ignored. These trade-offs however impact the quality of the results which are critical in determining whether the chip-to-chip transmission will happen according to the specifications.

Apache is sponsoring a workshop at DesignCon where several industry experts from semiconductor and system design houses including Larry Smith from Altera, Jim Antonelis from Broadcom, Rick Brooks from Cisco, and Dr. Souvik Mukherjee from Texas Instruments are coming together to discuss their understanding of these challenges, to present the approaches they are taking and to outline the needs they have for tools and methodologies. Additionally, a panel discussion will be conducted to foster discussion on the techniques for chip model creation, package and board extraction tools and co-simulation methodologies. Perspectives on system modeling, extraction and simulation using EM tools, methods of accurate and distributed modeling of the IC and techniques of performing time domain and frequency domain simulations will be shared through presentations addressing both power and signal integrity issues. The topics will include practical methods for designing and evaluating the system performance. Another important topic is to define a method to build confidence in these methods. This workshop will be an open forum to share insights, discuss issues and present proven techniques. Such an open exchange of ideas and information from semiconductor and system companies will help to define the content of future technologies for chip and package modeling and system level verification of power and signal integrity.

I hope you will join us in the workshop “Practical methodologies for Power/Signal Integrity of Chip-Package-Board Designs” held from 9AM to noon on Thursday February 4th at the DesignCon conference in Santa Clara Convention center.

For more information on the workshop, please visit http://www.designcon.com/2010/attendees/th_th1/index.asp

You can also register for complimentary Exhibit PLUS pass to DesignCon for entry to the workshop. http://www.apache-da.com/apache-da/Home/NewsandEvents/Events.html