Unlike traditional integrated circuit (IC) designs, multi-dimensional 2.5D and 3D ICs are composed of multiple individual chiplets, each built to a separate process node best suited for its specific purpose. There are many different design options for connecting these chiplets, and any or all of these approaches can be combined on a single 3D IC assembly. This results in multiple components of different materials integrated in all three dimensions, which creates new and unique verification challenges for 2.5/3D IC designers.

3D IC assembly flow

Multi-dimensional ICs are one part of the industry’s answer to moving beyond the limits of Moore’s law. While 2.5D approaches, particularly chiplets placed upon a silicon interposer, have gained broad adoption, the move to true 3D IC is still early in its design lifecycle. Design tools and best design practices continue to evolve and improve, but many challenges are yet to be resolved.

In a true 3D IC, early design and package planning can be a challenging task, as the specific approach, materials, and chiplet placements used will induce thermal and mechanical stresses that can impact the intended electrical behavior of the full assembly design (Figure 1). Selecting the optimal approach and optimal chiplet placements becomes critical, implying multiple iterations will be required to determine the best final design.

Figure 1. Packaged 3D IC with non-uniform power distribution.

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By: Abu Sebastian, Manuel Le Gallo-Bourdeau, Vijay Narayanan

The energy-efficient chip showcases critical building blocks of a scalable mixed-signal architecture.

A rendering of IBM’s analog AI chip.

We’re just at the beginning of an AI revolution that will redefine how we live and work. In particular, deep neural networks (DNNs) have revolutionized the field of AI and are increasingly gaining prominence with the advent of foundation models and generative AI. But running these models on traditional digital computing architectures limits their achievable performance and energy efficiency. There has been progress in developing hardware specifically for AI inference, but many of these architectures physically split the memory and processing units. This means the AI models are typically stored in a discrete memory location, and computational tasks require constantly shuffling data between the memory and processing units. This process slows down computation and limits the maximum achievable energy efficiency.
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Ansys is hosting IDEAS Digital Forum 2022, a premier virtual event bringing together industry executives and technical design experts to discuss the latest in EDA for Semiconductors, Electronics, and Photonics.

See the full online conference agenda and list of speakers here. No cost registration allows you to attend the event on December 6^th or on-demand at your convenience.

IDEAS kicks off with Keynote addresses from Intel’s Raja Koduri, Qualcomm’s Pankaj Kukkal, and surprising insights into the metaverse from DP Prakash with start-up Youtopian.

Keynote Speakers and Panelists at IDEAS on December 6^th, 2022

You can also attend the IDEAS Panel Discussion in the afternoon entitled “Thermal Management: How to Keep Your Cool When Chips Get Hot”. The Ed Sperling moderated panel discussion features Jean-Philippe Fricker from Cerebras, Roopashree HM from Texas Instruments, and Bill Mullen, senior director of R&D at Ansys.

8 technical tracks follow the Keynotes spanning Thermal Integrity, Power Integrity, Timing Closure, Electromagnetics, Machine Learning, Hardware Security, and Photonics. Over 30 technical presentations by real design engineers address case studies of their semiconductor, electronic, and optical designs from companies including:

Select authors will be available for Q&A chat with the event attendees after their presentations – don’t miss this opportunity to interact with industry experts.

To see the full agenda, Register now for IDEAS to add this premier event to your calendar.

Register now