Intel Foundry Unveils Breakthroughs in Transistor and Packaging Technologies at IEDM 2024

At the IEEE International Electron Devices Meeting (IEDM) 2024, Intel Foundry unveiled a series of pioneering advancements poised to reshape the semiconductor landscape for the coming decade. With innovations addressing transistor scaling, interconnect efficiency, and advanced packaging, Intel’s research highlights the company’s leadership in enabling the exponential growth of computing power required to meet artificial intelligence’s (AI) insatiable demands.

As AI continues to push the limits of existing technology, the need for energy-efficient, high-performance chips grows ever more critical. Intel’s latest breakthroughs mark significant steps in transistor miniaturization, interconnect materials, and assembly techniques—key ingredients for sustaining Moore’s Law and advancing toward a trillion-transistor chip by 2030.

“Our research at Intel Foundry is focused on overcoming the technological roadblocks of tomorrow,” said Sanjay Natarajan, Intel senior vice president and general manager of Intel Foundry Technology Research. “These advancements reflect our mission to deliver cutting-edge semiconductor innovations, developed domestically, to meet global AI demands and solidify U.S. manufacturing leadership under initiatives like the CHIPS Act.”

Breaking New Ground in Interconnect Technology

One of the headline innovations Intel presented was its use of subtractive ruthenium (Ru) for chip interconnects, a revolutionary step beyond copper. Traditionally, as transistors shrink and interconnects become denser, capacitance—the resistance to electrical flow—has been a key challenge, leading to slower performance and increased power consumption.

Intel’s subtractive Ru process addresses this head-on, achieving up to 25% capacitance reduction by introducing airgaps at line-to-line pitches of 25 nanometers or less. Unlike previous approaches that relied on costly lithographic techniques to create these airgaps, Intel’s process simplifies manufacturing and enhances scalability.

“With this innovation, we’re setting the stage for efficient interconnects at future nodes,” explained Natarajan. “Subtractive ruthenium represents a practical, cost-effective alternative to copper in the most challenging layers of chip design.”

Accelerating Advanced Packaging with Selective Layer Transfer

In the world of advanced packaging, Intel Foundry showcased its Selective Layer Transfer (SLT) technology—a breakthrough in chip assembly for heterogeneous integration. SLT delivers 100x faster throughput for chip-to-chip assembly, enabling the transfer of ultra-thin chiplets. This approach not only reduces chip size but also offers better flexibility and density compared to conventional chip-to-wafer bonding techniques.

For AI-driven applications, where modular architectures dominate, SLT provides a solution to enhance performance while reducing manufacturing complexity. Intel’s technology allows designers to create smaller, higher-functioning systems that are more power-efficient and cost-effective.

“Selective Layer Transfer is a game-changer for advanced packaging,” said Intel’s technical team. “It redefines how chiplets can be integrated, paving the way for highly modular, flexible architectures—perfect for AI workloads.”

Pushing Transistor Scaling to New Frontiers

To sustain Moore’s Law, Intel Foundry continued its work on gate-all-around (GAA) RibbonFET transistors, demonstrating industry-leading performance at an aggressively scaled 6-nanometer gate length. RibbonFET transistors, Intel’s version of GAA technology, deliver better electrostatic control and superior short-channel effects—critical for maintaining performance as dimensions shrink.

Looking even further, Intel unveiled progress on 2D gate-all-around field-effect transistors (FETs) using transition metal dichalcogenides (TMDs). These advanced materials are viewed as potential successors to silicon, offering better performance at extreme scales. Intel demonstrated NMOS and PMOS transistors with a gate length scaled to 30 nanometers, focusing on gate oxide module development to achieve improved energy efficiency and durability.

“With these advancements, we’re pushing the physical limits of transistors,” said an Intel researcher. “Our work with 2D FETs lays the groundwork for the post-silicon era.”

Gallium Nitride: Powering the Next Generation of Electronics

Intel’s IEDM presentation also included a first-of-its-kind demonstration of 300-millimeter gallium nitride (GaN) technology for power and radio frequency (RF) applications. Fabricated on a trap-rich silicon-on-insulator (TRSOI) substrate, Intel’s GaN transistors deliver superior performance at higher voltages and temperatures compared to silicon-based solutions. This innovation is particularly significant for power electronics and RF systems, where energy efficiency and signal integrity are paramount.

By reducing signal loss and improving linearity, Intel’s GaN-on-TRSOI platform sets the stage for future power-hungry applications like 5G, RF communications, and advanced automotive systems.

Toward a Trillion-Transistor Future

Intel Foundry’s advancements align with the industry’s overarching goal: building chips with 1 trillion transistors by the next decade. Achieving this requires simultaneous innovation across three critical domains:

1. Advanced memory integration to eliminate latency and bandwidth bottlenecks.
2. Hybrid bonding techniques to enhance interconnect bandwidth.
3. Modular system expansion with high-density connectivity solutions.

Intel also highlighted the need for transistors capable of ultra-low voltage operation—below 300 millivolts—to address the growing challenge of thermal bottlenecks. This innovation would result in a dramatic reduction in energy consumption and improved thermal management, enabling scalable AI computing.

A Call to Innovation

As the semiconductor industry navigates unprecedented demand for AI, Intel Foundry’s advancements stand as a testament to its role in driving innovation. By addressing challenges in transistor scaling, interconnects, and advanced packaging, Intel is laying the foundation for a new era of computing.

“These innovations are more than incremental steps,” said Natarajan. “They represent a fundamental shift toward enabling the next generation of AI-driven systems, ensuring that we stay ahead of the curve in a world where technology drives progress.”

Intel’s announcements at IEDM 2024 reaffirm the company’s position as a leader in semiconductor research and manufacturing. Backed by domestic initiatives like the CHIPS Act and a global commitment to innovation, Intel Foundry remains focused on delivering the building blocks of future AI systems.

For more details on Intel’s IEDM research, visit the official IEDM website.

Tags: Advanced Packaging, Intel Foundry, Selective Layer Transfer, Subtractive Ruthenium, Transistor Scaling, Trillion-Transistor Era

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