Winning doesn’t happen at the finish line, even in IC verification

David Abercrombie

By David Abercrombie

In motor car racing, many people think the win happens on the track, with lightning-fast pit stops ensuring the fastest car takes the black and white checkered flag at the finish line. In reality, the win happened long ago, in the garage, as the car was built and tested and rebuilt. The same is true in integrated circuit (IC) design. Getting a design through a successful tapeout on schedule isn’t just the result of signoff verification. It begins much earlier, back in the design and implementation stages. Finding and correcting critical errors in these early design stages helps design teams make adjustments quickly while layouts are still more open and flexible, avoiding time-consuming and complex fixes during signoff that can play havoc with delivery schedules.

But what happens when that early verification doesn’t match signoff verification? Despite all the work designers put in during the design stages, they may find themselves still trying to fix those hard errors, only now they’re constrained by layout restrictions, and under the gun to meet the schedule. Calibre® shift left (early design-stage) solutions bring industry-leading Calibre signoff-quality verification and design optimization into the design and implementation environments. Shift left verification and optimization can help design teams minimize those late-stage signoff iterations while still delivering high performance, high reliability designs. Using the same qualified rule decks and underlying engines used by the signoff toolsuite, Calibre shift left tools and technology deliver targeted verification that hones in on those errors most critical in early-stage designs, provide thorough analysis of complex design constraints, support designers with guided debugging to enable optimal fixes that remain signoff-compliant throughout the design flow, and apply selective automated design optimizations, all within a user-friendly toolset integrated into the designer’s design or implementation environment.

But just like every person in that race car garage has a different responsibility, different designers have distinct priorities and requirements. Intellectual property (IP) designers may be focused on eliminating symmetry and alignment issues, while block/full chip designers must manage multiple simultaneous verification flows quickly and efficiently, with the goal of reducing block integration errors and ensuring accurate routing and assembly as the full chip design comes together. 2.5/3DIC assembly designers also have unique needs—they must determine the optimal floorplan for an assembly and ensure that multiple chiplets produced on multiple process nodes (potentially by different foundries) can be integrated into a unified package that works seamlessly to deliver the intended performance and reliability.

How can shift left design-stage solutions achieve these diverse goals in a single toolset? By providing an integrated ecosystem of tools and processes that provide “right time/right size” design and verification while incorporating overall best practices and performance optimizations. The Calibre nmPlatform toolsuite is trusted across the industry to deliver the highest quality of signoff physical verification in IC design. The goal of Calibre shift left solutions is to deliver that same quality and trust wherever it is needed in the design enablement flow to help IC design companies move through the design and implementation processes faster, without compromising on the quality of their products.

Innovative tools and capabilities have been added to the Calibre toolsuite to help design companies begin verification and design optimization earlier in the design flow. Targeted rule sets automatically identify relevant and high-priority design-stage checks, helping designers eliminate critical and systemic errors before they can propagate throughout a layout. Integration with major design and implementation environments, coupled with user-friendly interfaces, ensure designers can perform design verification and optimization in familiar workspaces without time-consuming streamouts or tool changes. Because Calibre shift left tools use qualified Calibre rule decks, they deliver Calibre signoff-quality verification, ensuring that fixes remain Calibre-clean throughout the design flow. The same underlying engines that support Calibre signoff tools also support Calibre design-stage tools, ensuring optimal performance and reliability. Compared to the traditional design implementation flow, Calibre shift left solutions enable a more efficient and productive design-stage verification and optimization workflow that reduces tapeout schedules and enhances designer productivity (figure 1).

Figure 1. Calibre shift left solutions enable design teams to compress delivery schedules while boosting both designer productivity and design quality.

In addition to their reliance on qualified Calibre rule decks and underlying engines, another feature that makes the Calibre shift left solutions unique is their ability to focus on specific design-stage priorities for different designs (figure 2). The automated selection of targeted rulesets enables designers to perform signoff-quality verification for those issues most relevant to the design type they are working on. By limiting design-stage verification to critical and system issues, both runtimes and iterations are significantly reduced while designer productivity is enhanced.

Figure 2. Calibre shift left design-stage verification encompasses innovative tools and functionality that enables design teams to focus on relevant design-stage verification.

The value of implementing Calibre shift left solutions as part of the design and implementation flow are numerous.

Innovative tools that generate and run selective rulesets use a targeted set of checks to find and eliminate systemic errors, while ignoring checks that don’t provide substantive insight into early design-stage layouts.

Automated selection of targeted rulesets provides substantial benefits:

• 22-55% reduction in checks across a range of process nodes
  • Removes checks requiring heavy computational load
  • Removes context-dependent checks that flatten design hierarchy and scale poorly
  • Removes checks that don’t help find early systematic design issues
  • Removes checks that would return transitory or irrelevant errors
• Reduces runtime and memory consumption of design-stage verification iterations
• No rule deck modification required
• Smaller output databases
  • Fewer but more meaningful results speed up debug
• Eliminates time previously spent debugging transitory/irrelevant errors
• Identifying and resolving critical layout errors with signoff-level quality correction reduces the number of verification iterations and rework needed during signoff verification.
• By reducing the overall number of design verification runs and debug cycles needed, design teams have more time to advance the tapeout schedule and/or perform additional optimization/analysis to improve the physical quality and/or performance of the design by optimizing performance, power, and area (PPA).

Execution optimization provides automated run paradigms that guide designers to the most efficient fulfillment of their business/design objectives, while continuous optimization of the Calibre ecosystem delivers faster, more efficient setup and execution in all stages of the design and verification flow.

Debug optimization offers efficient and root-cause-centric error debugging with automated grouping and visualization to ensure errors are accurately identified, analyzed, and corrected.

Calibre correct-by-construction layout modification and optimization enhances manufacturability, performance, and reliability, while automated back-annotation ensures layout changes made in design and implementation stages are correctly included in the design database.

User-friendly interface tools provide designers access to qualified Calibre rule decks during the P&R/design phases, ensuring that adjustments and corrections made to the layout are Calibre-clean, reducing signoff verification iterations later on. These interfaces allow designers to run checks, debug results, apply changes, and re-verify in real time, within their familiar design or P&R environment.

Innovative tools and functionalities enable design-stage signoff-quality design for manufacturing (DFM) layout enhancements, such as via and metal insertion, as well as decoupling capacitor (DCAP) and filler cell insertion.

Best practices for the use of the Calibre platform and tools. Continual process improvements across the Calibre toolsuite enable design teams to operate more efficiently by making best practices inherent in the flow, rather than a conscious and learned behavior on the part of design teams.

Improved PPA metrics: By verifying chips with signoff accuracy earlier in the design process, designers can ensure they meet performance, power, and area (PPA) targets, reducing the risk of design failures and re-manufacturing.

Guiding design teams to the most efficient use of their time and resources while maintaining or improving results is the goal of all EDA companies. Just like race car designers and mechanics want to deliver the best car to the starting line, Calibre shift left solutions helps design teams deliver the best IC designs on schedule. By accessing the same Calibre signoff-quality analysis, verification, and optimization functionality within an innovative portfolio of design-stage solutions, designers can now more quickly and confidently find and eliminate systematic and targeted design errors during design implementation, and apply selective correct-by-construction layout optimizations, compressing the design stage to get to final signoff sooner with higher-quality layouts.

For more about the tools and processes that comprise the Calibre shift left solutions, visit Shift left solutions for IC design stage verification at Siemens EDA. Our comprehensive resource library contains technical papers, videos, product factsheets, and more.

About Author

David Abercrombie is the marketing director for Calibre multi-patterning, machine-learning, and licensing applications at Siemens EDA, a part of Siemens Digital Industries Software. David drives the roadmap for developing new and enhanced EDA tools to solve the growing challenges in advanced physical verification and design for manufacturing (DFM). Prior to joining Siemens, David managed yield enhancement programs in semiconductor manufacturing at multiple companies. He is extensively published in papers and patents on semiconductor processing, yield enhancement, and physical verification. David received his BSEE from Clemson University, and his MSEE from North Carolina State University. He may be reached at david.abercrombie@siemens.com.

Tags: Caliber, Siemens

This entry was posted on Monday, February 19th, 2024 at 12:18 am. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.