The value of a shift left strategy in IC design

By David Abercrombie and Michael White

No matter what process node you’re working at, or how big or how complex your integrated circuit (IC) design is, design enablement is a complex process that goes through multiple stages. The faster you get your design to market, the better your chances of achieving your market goals. But getting your design to the foundry on schedule, while ensuring the final product will not only be manufacturable, but also provide the intended performance and reliability, all depends on achieving and maintaining high productivity and quality of results throughout the design flow.

IC design companies, like any other business, constantly look for ways to improve and speed up their processes. One approach that has recently gained significant traction is the idea of “shifting left”—performing design layout verification and optimization earlier in the design flow, instead of waiting until the signoff verification stage. However, simply shifting signoff physical verification to earlier stages of the design flow is neither practical nor productive. Signoff verification is intended to apply to full chip designs where all components are complete and connected. Running signoff verification on incomplete or “dirty” designs is not only time-consuming, but also returns millions of errors, many of which are irrelevant, as they are caused by the incomplete nature of the layout. Hardly the increase in productivity the design companies were hoping for.

An effective shift left strategy takes a holistic approach that seeks to optimize the entire design flow. Design companies hoping to achieve the full benefit of a shift left approach should start by understanding their own needs and goals, and how a shift left implementation changes their design flow methodology to help them succeed. The gist of the shift left philosophy is to reduce signoff iterations by shifting some physical verification analysis into earlier stages of the design flow, where errors in each component can be corrected more quickly and easily. However, note the use of the word “some.” The central idea of a shift left strategy is to find and correct critical and systemic errors before they are propagated throughout a design. By eliminating these errors “at the source,” thousands of errors can be avoided during signoff verification.

What, then, is the difference between shift left verification and the layout verification offered by custom design or place and route (P&R) tools? Simply this—shift left design-stage verification relies on tools and verification functionality that are intentionally designed to provide targeted verification and optimization in a user-friendly environment, with full access to foundry-preferred rule decks and performance engines to provide signoff-quality results in the most efficient manner. Instead of the comprehensive coverage of signoff verification, shift left verification automatically selects a set of targeted checks chosen to address known and typical critical design-stage issues. By focusing on the identification and resolution of these issues, design teams immediately reduce runtimes and debug cycles. Because the tools rely on foundry-preferred rule decks and signoff verification engines, errors are debugged and fixed using signoff requirements, meaning they will not reoccur during signoff verification. Automated back-annotation ensures that all layout changes are safely and accurately incorporated into the design database.

Of course, there’s even more that goes into making shift left verification a useful and practical process. Knowing that IC designers and P&R engineers are not necessarily physical verification experts or familiar with verification tools, effective shift left implementation provides a user-friendly environment that simplifies and speeds up setup, with automation run invocation and resource forecasting for efficient resource use and faster runtimes. Advanced and innovative verification functionality, such as equation-based design rule checking, intelligent pattern matching, advanced property extraction and clustering, automated waivers, early short isolation, symmetry verification, and gray-boxing of missing or incomplete components, augments the selective checks to further reduce verification runtimes and eliminate errors that are irrelevant to design-stage verification. Minimizing, grouping, and visualizing error results in intuitive, user-friendly formats, supplemented by automated root cause analysis, can dramatically improve the efficiency of and reduce the time required for debug and correction. Integration with design and P&R tools enables design companies to build a best-in-class tool solution that allows their staff to work in a familiar environment while achieving signoff-quality results.

A complete shift left strategy also incorporates selected design for manufacturing (DFM) layout optimizations to improve performance and reduce the chances of manufacturing failures. Implementing analysis-based, correct-by-construction layout optimizations during IC design and implementation can improve power management earlier in the design flow (when it’s easier to make adjustments) and prepare designs for signoff verification faster. Typical shift left layout optimizations include:

• Automated via insertion to reduce voltage (IR) drop and moderate the impact of via resistance on manufacturability and reliability
• Parallel run length insertion that automatically finds open tracks and inserts metal and vias to create parallel runs to lower resistance on power grid structures
• Automated insertion of filler cell and decoupling capacitor (DCAP) cell insertion in IC layouts after design implementation to prepare designs for signoff verification

IC design companies must chase an increasingly complex list of requirements to deliver their chips to a market that continuously demands greater functionality, reliability, and performance, not to mention improved efficiency, power usage, and product life. So why aren’t all design companies already using shift left tools and techniques? Shift left verification isn’t required by anyone—companies adopt shift left strategies based on their potential to deliver performance and value. But by freeing up design and implementation tools from functions they were never intended or designed to perform, and using tools designed from the ground up to provide targeted, relevant, signoff-quality design-stage verification and optimization, design companies can quickly realize the full benefit of finding and eliminating critical design issues before they are “baked into” the full chip layout.

With a clear understanding of the purpose and intent of a shift left strategy, and best practices for the use of shift left tools and processes, design companies can achieve significant increases in productivity while delivering higher quality designs to market faster.

For more information and additional resources on how a shift left strategy can help your organization become more productive, visit our website, Shift left with Calibre solutions.

Authors

David Abercrombie David Abercrombie is the marketing director for Calibre multi-patterning, machine-learning, and licensing applications at Siemens EDA, a part of Siemens Digital Industries Software. David drives the roadmap for developing new and enhanced EDA tools to solve the growing challenges in advanced physical verification and design for manufacturing (DFM). Prior to joining Siemens, David managed yield enhancement programs in semiconductor manufacturing at multiple companies. He is extensively published in papers and patents on semiconductor processing, yield enhancement, and physical verification. David received his BSEE from Clemson University, and his MSEE from North Carolina State University.

Michael White Michael White is the senior director of physical verification product management for Calibre Design Solutions at Siemens EDA, a part of Siemens Digital Industries Software. Prior to Siemens, he held various product marketing, strategic marketing, and program management roles for multiple semiconductor companies, as well as the Lockheed Skunk Works. Michael received a B.S. in System Engineering from Harvey Mudd College, and an M.S. in Engineering Management from the University of Southern California.

Tags: Calibre

Category: Chip Design

This entry was posted on Friday, September 1st, 2023 at 12:24 pm. You can follow any responses to this entry through the RSS 2.0 feed. Both comments and pings are currently closed.