By Prakash Narain, President & CEO, Real Intent
Prakash Narain
Functional verification will become increasingly critical in chip and SoC design methodologies, with the three traditional workhorses for early functional verification — simulation, formal verification, and static sign-off — all extensively deployed.
Functional verification will continue its shift left. To help achieve this, static sign-off technologies must ensure adherence to specific methodology rules designed to further reduce complexity. For example, the connectivity and glitch sign-off domain has rules for early verification of block abutment for more efficient physical design. Additionally, new failure modes requiring static sign-off will emerge, due to the continuing increase in design complexity. In addition to clock domain crossing, and reset domain crossing sign-off, we will be seeing more design initialization and low-power sign-off.
