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Sanjay Gangal
Sanjay Gangal
Sanjay Gangal is a veteran of Electronics Design industry with over 25 years experience. He has previously worked at Mentor Graphics, Meta Software and Sun Microsystems. He has been contributing to EDACafe since 1999.

EDACafe Industry Predictions for 2023 – Real Intent

 
January 23rd, 2023 by Sanjay Gangal

By Prakash Narain, President & CEO, Real Intent

Prakash Narain

Functional verification will become increasingly critical in chip and SoC design methodologies, with the three traditional workhorses for early functional verification — simulation, formal verification, and static sign-off — all extensively deployed.

Functional verification will continue its shift left. To help achieve this, static sign-off technologies must ensure adherence to specific methodology rules designed to further reduce complexity. For example, the connectivity and glitch sign-off domain has rules for early verification of block abutment for more efficient physical design. Additionally, new failure modes requiring static sign-off will emerge, due to the continuing increase in design complexity. In addition to clock domain crossing, and reset domain crossing sign-off, we will be seeing more design initialization and low-power sign-off.

Each of the three functional verification workhouses must manage even higher design complexity and capacity requirements by supporting hierarchical analysis. This hierarchical analysis requires accurate abstraction, with custom hierarchical analysis needed for each application. For example, different clock-domain crossing (CDC) abstraction models can have different ranges of accuracy, while reset domain crossing (RDC) abstraction models require a more complex, database-driven approach.

Static sign-off must also accommodate multiple modes of operation for each application. Hierarchical multimode analysis means different things for different domains. CDC analysis must support multiple clock modes, along with exclusive relationships between asynchronous clocks. RDC analysis must support multiple scenarios, RTL linting will support multiple policies, and DFT analysis will have multiple test modes. All multimode analyses must produce consolidated reports.

Category: EDA Predictions

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