Verification 3.0: Grab Your Surfboards, the Next Big Wave is Coming

I’m that rare person, a native (even second generation) Californian, and grew up going to the Southern California beaches during the summers.  I earned my Red Cross lifeguarding certificates, and was a pretty good bodysurfer in my youth.  The greatest adrenaline rush I’ve ever had is catching a wave so perfectly that I was in the pipeline, not on a surfboard, but just my body half in, half out of the wave.  So, when Joe Costello opened up the inaugural Verification 3.0 Innovation Summit (V3IS) with analogies about waves and rip tides and bodysurfing, he was speaking both my languages, verification and oceans.  There’s a new verification wave coming, Joe said, building strength and speed, and we should be preparing to have a glorious ride to the shore.  The alternative, to not recognize this wave, is to be caught in the rip tide, the undercurrent, with dire consequences.

Image source: Good Free Photos

Joe, and the more than a dozen speakers and companies that spoke and exhibited at V3IS (held last week in Silicon Valley), talked about the various driving factors and technical and business components of this next generation of verification, and also about the previous two generations of verification methodology and tools.

The first generation of DV was roughly the 1980s and 1990s, and included the advent of RTL simulation tools.  Directed tests – each meant to verify only a specific feature of the design – were a key component of this generation.  This generation also saw the start of the large EDA companies, with Cadence, Mentor and Synopsys all getting their start in this era.  Joe Costello, as CEO of Cadence for most of this period, was one of the key figures driving the adoption, deployment and success of Verification 1.0.

Increasing chip complexity – Systems on Chips (SoCs) – drove Verification 2.0 through the 2000s and 2010s.  This generation saw verification technology advance with new tools complementing and supplementing simulation and directed tests.  These included constrained random test generation, functional coverage, assertion checking, formal verification and more.  The big success of Verification 2.0 was the quantum increase in first chip success, with this metric increasing from about 40% at the end of Verification 1.0 to over 90% for Verification 2.0 adopters.  Methodology was standardized with the adoption of UVM.  Verification 2.0 also had a business change versus the first generation:  the migration of the business model from perpetual licenses to time-based or subscription licenses.

As the VP worldwide sales for Verisity Design I played some role in the adoption, deployment and success of Verification 2.0.  Verisity’s Specman product was arguably the cornerstone of Verification 2.0, and the “e” language reuse methodology (eRM) was clearly the forerunner of UVM.  Verisity caught that Verification 2.0 wave almost perfectly.

As with the motivation for Verification 2.0, this third generation is driven by exponentially increasing complexity.  Some of the new complexity comes from the new domain specific architectures (DSAs) that require additional verification to achieve the required production quality.  These new architectures include open instruction set architectures for processors, such as RISC-V, and architectures for AI.  Some of the new complexity comes from having more than a single piece of silicon that needs verifying together.  And some of the complexity comes from the fact that with current SoCs and systems, the verification of the hardware cannot be separated from the verification of the software.

This complexity requires new methodology, technology and tools, and new hardware resources to run the tools.  While Verification 2.0 saw the evolution from workstations on desktops to company-owned compute farms, these compute farms do not have sufficient resources for Verification 3.0.  However, the cloud computing resources now available to the community at large do have the capacity, and the growth plans, to support Verification 3.0.  Also, with cloud computing comes the business evolution, from subscription licenses to software as a service (SaaS).

The new methodology and tools for Verification 3.0 are still evolving.  Some of the tools come from technologies that have been around for a number of years, such as test generation, formal verification and instruction accurate simulation for software (virtual platforms).  Some of the tools are coming from relatively new technologies, such as the Portable Stimulus Specification (PSS).  All these technologies need to support the DSAs, work on the cloud, support the SaaS business model and be open enough to enable collaboration across the community.  Because community collaboration – between semiconductor vendors, systems companies, tool developers, IP providers – is needed to develop this third-generation methodology.

My current company, Imperas Software, is participating in Verification 3.0 by supporting RISC-V with open source models of RISC-V processors, and flows for architectural optimization, compliance checking, design verification, software development and hardware-software co-verification. In supporting the RISC-V compliance work we also recently announced riscvOVPsim which is available for FREE on GitHub as a reference Instruction Set Simulator (ISS), including open source model, specifically for the RISC‑V community of software developers, implementers and early adopters.

The third wave of verification is getting ready to break; let’s ride this one to shore.

Tags: Imperas, RISC‑V, Verification

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