The news about Intel Foundry takes center stage this week. Prior to summarizing the Intel announcement, here’s a short comment. Before Pat Gelsinger took office as the company’s CEO, some investors suggested Intel to adopt the fabless model, just like AMD in 2008. Gelsinger, instead, doubled down on manufacturing, announcing not just his intention to keep the fabs, but even to offer a foundry service. Intel’s decision to separate the financial reporting for the two parts of its business – foundry service VS chip sales – is probably an unavoidable step in the implementation of Gelsinger’s strategy, and will put it to the test. On the one hand, the new reporting structure will force Intel Products (the chip sales business) to correct its inefficiencies, as it will lose the convenience of easy access to internal manufacturing resources and seemingly costless design respins. On the other hand, Intel Foundry will be forced to quickly become competitive against TSMC, also because – at least officially – Intel Products will now be free to choose any other foundry instead. As of today, an unavoidable side effect of this decoupling is the public disclosure of Intel Foundry’s substantial losses. Will Intel Foundry deliver on its promise of reaching breakeven around 2027? It would be interesting to know if Intel has a plan B, and – if so – if plan B involves going fabless as an extreme option. The new financial reporting structure makes it easy to spot the lossy business within Intel (if any), and this easy spotting capability may sound like setting the stage for divestiture. A key difference from 2008, however, is the current chip war economy, with taxpayers around the world currently subsidizing their respective domestic semiconductor industries. Depending on the dose, public subsidies can offset a company’s inefficiencies and make it competitive on the market. Let’s now move to the Intel announcement and other related news.

Intel’s financial reporting structure to separate Foundry from Products

On April 2, Intel outlined a new financial reporting structure that is aligned with the company’s previously announced foundry operating model. The new reporting structure establishes a foundry relationship between Intel Foundry, the company’s manufacturing organization, and Intel Products, comprised of the company’s product business units. Beginning with the first quarter 2024, Intel will present segment results aligned to the following operating segments: Client Computing Group (CCG); Data Center and AI (DCAI); Network and Edge (NEX); Intel Foundry; Altera; Mobileye; and Other. CCG, DCAI and NEX will collectively be referred to as Intel Products; Altera, Mobileye and Other will collectively be referred to as All Other. Under this new structure, Intel Foundry will recognize revenues generated from both external foundry customers and Intel Products, as well as technology development and product manufacturing costs historically allocated to Intel Products. Instead of recognizing manufacturing costs that were previously allocated to the product operating segments, Intel Products will be charged a market-based price by Intel Foundry. Following the adoption of this new reporting structure, Intel filed a new Form 8-K containing recalculated operating segment results for the years 2023, 2022 and 2021.

Read the rest of New Intel financial reporting structure highlights Intel Foundry’s loss of $7B in 2023

Is pain a positive thing for character-building? Or is it just that humans instinctively need to find a reason to justify pain? Quite an off-topic question here – but not that much, after all, if it stems from a speech given by Nvidia CEO Jensen Huang. For his take on character-building, see the “Further reading” paragraph at the end of this week’s news roundup. But first, some on-topic technology updates.

New Synopsys announcements from SNUG Silicon Valley

Here’s a quick overview of some of the announcements Synopsys made on occasion of its recently held annual Synopsys User Group (SNUG) conference in Silicon Valley. In the area of multi-die designs, 3DSO.ai is a new AI-driven capability built natively into Synopsys 3DIC Compiler, a unified exploration-to-signoff platform. 3DSO.ai offers optimization for signal integrity, thermal integrity, and power-network design. Also targeted at multi-die designs, Synopsys Platform Architect – Multi-Die accelerates design timelines, delivering – according to the company – a six to twelve month “shift left” from RTL for the analysis of performance and power, while accounting for the interdependencies between multiple dies and allowing early partitioning decisions. Synopsys also unveiled two new hardware-assisted verification solutions: ZeBu EP2, the latest version in the ZeBu EP family of unified emulation and prototyping systems; and HAPS-100 12, Synopsys’ highest capacity and density FPGA-based prototyping system. Additionally, the company introduced Synopsys Cloud Hybrid solution, which enables users to burst from on-prem data centers to the cloud during peak needs – automatically splitting the job based on available capacity and eliminating manual data transfers. Lastly, Synopsys announced that it has completed the acquisition of Netherland-headquartered Intrinsic ID, a provider of Physical Unclonable Function (PUF) IP.

Altair to extend its meshless technology to electronics

Altair has announced the upcoming release of Altair SimSolid for electronics – promising fast, easy, and precise multi-physics scenario exploration for electronics, from chips to PCBs and full system design. SimSolid is an already existing Altair product, which so far has gained adoption in industries such as aerospace and automotive. According to the company, SimSolid’s main benefit is its ability to eliminate geometry simplification and meshing, the two most time-consuming and expertise-intensive tasks done in traditional finite element analysis. As a result, it is up to 25x faster than traditional finite element solvers, and effortlessly handles complex assemblies. Extending Altair SimSolid’s meshless technology to electronics will enable the tool to tackle intricate challenges like signal integrity, power integrity, and electromagnetic compatibility/interference, all while making simulations more accessible and efficient.

Read the rest of SNUG announcements; meshless multiphysics simulation; flaws in AI-generated RTL; open-source alternative to CUDA; skyrmion-based memory

Not just GPU-based acceleration: the partnerships announced on occasion of this year’s GTC event demonstrate that Nvidia software, too, is a key technology in several existing or upcoming EDA tools

EDA and engineering software received quite a bit of attention at the recent Nvidia GTC event, with “rockstar” CEO Jensen Huang mentioning this theme during his two-hour long keynote, and with some of the major vendors (namely Ansys, Cadence, Siemens – the German parent company, not Mentor – and Synopsys) issuing GTC-related press releases to announce their extended collaboration with Nvidia. While partnerships between Nvidia and EDA vendors are not new, this level of emphasis from both sides seems unprecedented and deserves a closer look.

The announcements issued by EDA and engineering software vendors highlight three main areas of collaboration with Nvidia: GPU-based acceleration; Omniverse-based visualization; and the use of AI development tools encompassed by the Nvidia “AI Foundry” offering. A fourth area, the only one specifically related to the EDA flow, is optical proximity correction based on Nvidia cuLitho.

Software acceleration based on Nvidia GPUs

In GTC-related announcements, the use of Nvidia GPUs for software acceleration was highlighted by Ansys, Cadence and Synopsys. Ansys harnesses Nvidia H100 Tensor Core GPUs to boost multiple simulation solutions, and prioritizes the new Nvidia Blackwell-based processors and Nvidia Grace Hopper for products across its portfolio – including Ansys Fluent, Ansys LS-Dyna, and its electronics and semiconductor products. As for Cadence, previously announced collaborations with Nvidia include the GPU-optimized Fidelity CFD (computational fluid dynamics) software and the Millennium Enterprise Multiphysics Platform, a hardware box for the acceleration of CFD simulations based on Nvidia GPUs. Synopsys is applying Nvidia accelerated compute architectures, including the GH200 Grace Hopper, across its full EDA stack spanning design, verification, simulation and manufacturing. The tool list includes Synopsys VCS, Synopsys Fusion Compiler, Synopsys PrimeSim, Synopsys Proteus (see below).

Read the rest of Nvidia’s role in the EDA industry

Will “programmed logic” (that is, GPUs and deep learning accelerators) give way to “hard-wired logic” in artificial intelligence applications? Taalas, a startup recently emerged from stealth, has no doubt about that (see the news below). Meanwhile, programmed logic keeps advancing – with Cerebras doubling down on its wafer-scale approach and launching a four trillion transistor chip. Other news this week, besides Taalas, contribute to the feeling that the end of geometrical scaling won’t stop IT advancements. That includes chiplet-based solutions, of course, but also new transistor types.

Hard-wired AI models promise a 1000x improvement in computational power and efficiency

Toronto-based Taalas has recently exited stealth mode and raised $50 million dollars over two rounds of funding led by Pierre Lamond and Quiet Capital. The company’s mission is to develop an automated flow for rapidly implementing all types of deep learning models (transformers, SSMs, diffusers, MoEs, etc.) in silicon. According to the company, proprietary innovations enable one of its chips to hold an entire large AI model without requiring external memory. Taalas claims that the efficiency of hard-wired computation enables a single chip to outperform a small GPU-based data center, opening the way to a 1000x improvement in the cost of AI. “The path forward is to realize that we should not be simulating intelligence on general purpose computers, but casting intelligence directly into silicon. Implementing deep learning models in silicon is the straightest path to sustainable AI,” said Ljubisa Bajic, Taalas’ CEO. Prior to co-founding Taalas, Bajic founded Tenstorrent in 2016.

Intel outlines a UCIe-3D solution

In a paper recently published on Nature Electronics, a team of Intel researchers propose a solution for using the UCIe standard in the three-dimensional integration of chiplets. According to the authors, their architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm. Research findings include that – contrary to trends seen in traditional signalling interfaces – the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. The Intel vision is that two chiplets will connect using multiple independent modules, with each UCIe-3D PHY directly controlled by the Network-on-Chip controller. To realize this vision, the authors anticipate challenges in the areas of cooling, power delivery and reliability. Advances in electronic design automation will be necessary, too.

Read the rest of Hard-wired AI models; UCIe in 3D packages; reconfigurable FETs; Samsung’s HBM3; Silicon Box in Italy

The U.S. government is reportedly asking the Netherlands, Germany, South Korea and Japan to put in place additional restrictions on exports to China. Japan is being asked to limit exports of chemicals such as photoresist, the Netherlands to stop ASML from servicing and repairing lithography equipment installed in China before limits on sales were put in place. Moving to this week’s news roundup, the trend towards convergence between EDA and the rest of engineering software continues – with Cadence’s acquisition of Beta CAE. Even though much smaller in financial terms ($1.24 billion), this move can be likened to the recent Synopsys’ acquisition of Ansys.

Cadence acquires structural analysis tool vendor Beta CAE

Cadence has entered into a definitive agreement to acquire Switzerland-based Beta CAE, a leading provider of structural analysis and multi-domain simulation solutions. Beta CAE has a strong presence in the automotive industry. Its flagship products include Ansa, a multidisciplinary CAE pre-processor, and Meta, a multidisciplinary CAE post-processor. Additionally, Beta CAE’s Epilysis and Fatiq solvers are used in structural analysis and optimization problems, while the SPDRM (simulation, process, data, and resources management) tool manages the CAE processes. According to Cadence, Beta CAE’s products are very complementary to Cadence’s multiphysics system analysis portfolio – which includes Clarity, Celsius, Sigrity, Voltus, Fidelity and the recently announced Millennium M1 multiphysics platform.

Altera gets its name back after eight years

Following last October decision to operate its Programmable Solutions Group as a standalone business, Intel has recently rebranded it as “Altera”. In other words, the entity is getting its original name back. Intel bought FPGA vendor Altera in 2015 and dropped its name. Now this famous brand will reappear, with the addition of “An Intel Company”. Led by CEO Sandra Rivera, Altera is now seeking additional growth opportunities in AI applications. The company has preannounced a new product series called Agilex 3 – a low-power line of FPGAs aimed at low-complexity functions for cloud, communications and intelligent edge applications. Intel plans to hold a public offering for stock in Altera over the next two to three years.

Read the rest of Cadence acquires Beta CAE; Altera gets its name back; EDA standard updates; ChatGPT-generated Verilog code

Research papers make up a large part of this week’s news roundup, some of them from the recently held ISSCC or from SPIE 2024 Advanced Lithography + Patterning Conference. But first, some updates on US and Japan’s efforts to revive their respective semiconductor industries, and some financial results.

US CHIPS Act funding applications far exceed available resources

U.S. Secretary of Commerce Gina Raimondo has recently provided some updates on the implementation of the CHIPS and Science Act. In total, applicant companies have requested more than $70 billion in federal subsidies, roughly twice the amount of funding that is available, she said. Therefore, in her conversations with chips company CEOs asking for a certain amount of funding, Raimondo tells them “You will be lucky to get half of that.” Raimondo also said the department is prioritizing projects that will be operational by 2030. U.S. Secretary of Commerce reiterated the CHIPS Act’s goal: “We think our investments in leading-edge logic chips, leading-edge logic chip manufacturing, will put this country on track to produce roughly 20% of the world’s leading-edge logic chips by the end of the decade,” she said. “Today we are at zero.”

Japan updates: TSMC, Tenstorrent

TSMC has recently held an opening ceremony for its majority-owned subsidiary Japan Advanced Semiconductor Manufacturing (JASM) in Kumamoto Prefecture, Japan. Market research firm TrendForce forecasts the plant’s total capacity to hit 40–50K wafers per month, focusing mainly on 22/28-nanometer processes with a dash of 12/16-nanometer, paving the way for the next phase of the Kumamoto expansion. The Japanese government has reportedly said it will give TSMC up to $4.86 billion more in subsidies to help it build a second chip fabrication plant in the country.

US-headquartered AI chip developer Tenstorrent has announced a partnership deal with Japan’s Leading-edge Semiconductor Technology Center (LSTC), which selected Tenstorrent’s Risc-V and chiplet IP for its edge 2-nanometer AI accelerator. In addition to the IP licensing portion of this deal, Tenstorrent will work with LSTC to co-design the chip. Under this project, Tenstorrent will also work with Japan-based Rapidus, which is planning to offer – besides chip fabrication – also advanced packaging technologies.

Market research firm TrendForce is optimistic about Japan’s chances to regain a leading position in the semiconductor industry, thanks to its equipment/material suppliers (TEL, JSR, Screen, Sumco, Shin-Etsu), availability of talent and water, a growing presence of TSMC which includes a 3D IC research center and plans for further plants.

Read the rest of CHIPS Act updates; Japan advancements; record Nvidia results; high-NA EUV ecosystem

What’s cooking at Arm after the recent, emboldening surge in its market capitalization? On the one hand, the company has unveiled two initiatives aimed at taking center stage in the emerging chiplet-based market and ecosystem. On the other hand, Masayoshi Son – CEO of SoftBank Group, the Japanese holding company that owns a 90% stake in Arm – is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia, with a potential help from Middle Eastern investors. Should this be confirmed, some questions would arise. Why would SoftBank challenge Nvidia? After all, the surge in Arm’s market capitalization seems to be an effect of the role played by Arm CPUs in Nvidia-based AI solutions. Does SoftBank feel that the pervasiveness of Arm CPUs is an advantage position enabling it to pursue additional AI opportunities, besides Nvidia? Will Arm continue to be a pure-play, neutral IP provider, if SoftBank gets involved in a “chip venture”? As for the Middle Eastern potential investors, the report does not mention any country names, but if it were Saudi Arabia or the UAE then SoftBank would be knocking on the same doors as OpenAI’s Sam Altman – who is also reportedly hoping to raise money from investors in that geography, for his gigantic semiconductor plan. Should those investors actually agree on satisfying all these requests, the role of Middle East in semiconductor funding would become an additional geopolitical factor to consider in the context of the current “chip war”. And now, let’s move to the news.

SoftBank reportedly planning a “chip venture”

SoftBank Group’s CEO Masayoshi Son is reportedly looking to raise up to $100 billion for a chip venture that will rival Nvidia. According to the report, the project – code named Izanagi – will supply semiconductors essential for artificial intelligence. SoftBank would inject $30 billion in the project, with an additional $70 billion potentially coming from Middle Eastern institutions.

Read the rest of Arm’s chiplet initiatives; SoftBank reportedly planning a chip venture; new Siemens Veloce systems; new ADC architecture

Let’s start with some comments, before getting to the news. Renesas’ acquisition of Altium will create a new, arguably unprecedented type of “bundle offer” targeted at system makers, by combining a portfolio of building blocks (chips) with a cloud-based software platform that is expected to reduce the system integration effort to put those blocks together. Will this help Renesas to sell more chips? Will this help Altium to sell more licenses? An obvious observation is that a system usually requires chips from a number of different vendors, so it’s not clear how a “privileged” relationship between a PCB design tool and just one specific chip vendor could benefit users. Unless the combined offering aims at making design system easier and more efficient for any choice of chips, including the ones that compete against Renesas products. But if this the case, it’s not clear how this could benefit Renesas. As for the impact of this acquisition on the EDA industry, it could be noted that Japan-headquartered Renesas is now directly competing against another Japanese company – Zuken – in the area of PCB design tools.

Another interesting news concerns Nvidia, reportedly building a new business unit to design bespoke chips for customers such as the hyperscalers. Waiting for more details, it can be observed that the hyperscalers internally developing their own AI chips seem to have made this decision also to gain independence from Nvidia, not just because they want tailor-made chips. In addition to that, one could ask if a new offering of bespoke GPUs could contribute to solving the GPU shortage – given the current global foundry capacity. OpenAI’s Sam Altman, who is on a mission to raise money to build new fabs, clearly thinks that the bottleneck is insufficient foundry capacity. And now, let’s move to the news.

Read the rest of Renesas to buy Altium; Nvidia to reportedly offer bespoke chips; Quilter’s AI-based PCB design tool; Cadence 2023 results

Going public has proven to be a good choice for Arm so far. As reported by Reuters, Arm’s share price increased by more than 30% on February 7 on the strong forecast the company announced on occasion of its last quarter results. Arm’s shares are now reportedly traded at twice the price of the initial public offering. Arm’s results are part of this week’s news roundup; but first, some EDA updates.

EDA updates: Cadence, Ansys, SignatureIP, Accellera

Challenging multiphysics incumbents such as Ansys, Cadence has announced its Millennium Enterprise Multiphysics Platform, what it claims is the industry’s first hardware/software accelerated digital twin solution for multiphysics system design and analysis. The first-generation Millennium M1 accelerates high-fidelity computational fluid dynamics (CFD) simulations, mostly targeting the simulation of complex mechanical systems. Available in the cloud or on premises, this solution includes GPUs from “leading providers”, and a Cadence Fidelity CFD software stack optimized for GPU acceleration and generative AI. Millennium M1 instances can be fused into a unified cluster, enabling near-linear scalability.

The latest release from Ansys, 2024 R1, includes a new user interface and a number of other improvements. As for electronics applications, Ansys claims that this release offers significant advances in simulation performance, meshing, and automated workflows. It covers various applications such as combined chip-package-PCB simulation, RF, HPC, 3D IC, and electric motors. New capabilities include ECAD-MCAD integration in Ansys Maxwell for flex and rigid PCBs, adaptive templates in Ansys Motor-CAD, and multi-solver interoperability for multiphysics and multiscale solutions.

Read the rest of Cadence’s Multiphysics Platform; Arm’s record numbers; stretching the capabilities of standard packaging

Confirming the growing importance of thermal aspects in electronic design, this week’s news roundup opens with two EDA announcements in this area. South Korea is also in the news with Samsung’s 3-nanometer updates and the country’s “mega cluster” plan.

Thermal design solutions from Cadence and Siemens EDA

Cadence has announced Celsius Studio, what it claims is the industry’s first complete AI thermal design and analysis solution for electronic systems. Celsius Studio addresses thermal analysis and thermal stress for 2.5D and 3D-ICs and IC packaging, in addition to electronics cooling for PCBs and complete electronic assemblies. According to Cadence, current product offerings in the area of thermal design consist mostly of disparate point tools, whereas Celsius Studio is a unified platform that lets electrical and mechanical/thermal engineers concurrently design, analyze and optimize product performance without the need for geometry simplification, manipulation and/or translation. Celsius Studio aims at system-level thermal integrity, converging electro-thermal co-simulation, electronics cooling and thermal stress. It was made possible by Cadence’s acquisition of Future Facilities in 2022.

Siemens EDA’s latest updates to Simcenter Flotherm software for electronics cooling simulation includes the “Embeddable Boundary Condition Independent Reduced Order Model” (BCI-ROM) technology, which allows a semiconductor company to generate an accurate model that can be shared with their clients for use in downstream high-fidelity 3D thermal analysis without exposing the IC’s internal physical structure. Siemens EDA introduced BCI-ROM in this October 2023 article.

Read the rest of New thermal EDA solutions; Samsung’s 2nd generation 3nm process; Infineon’s automotive deals; YMTC in Pentagon’s crosshairs