Governments around the world keep subsidizing their respective domestic semiconductor industries, with the most recent announcements coming from China and South Korea. Meanwhile, artificial intelligence is accelerating human brain research, with Google spearheading this effort. But first, a few EDA-related updates.

Siemens’ IP quality assurance solution

Siemens Digital Industries Software has introduced Solido IP Validation Suite software, an automated signoff solution for quality assurance across all design intellectual property types, including standard cells, memories and IP blocks. The suite – which includes Siemens’ Solido Crosscheck software and Solido IPdelta software – aims to shorten the time-consuming task of validating IP across all its design views such as logical, physical, electrical, timing, and power analysis contexts. It also provides version-to-version IP qualification for more predictable full-chip IP integration cycles and faster time-to-market.

Siemens’ PyTorch-to-RTL solution for AI accelerator design

Siemens Digital Industries Software has announced Catapult AI NN software for High-Level Synthesis of neural network accelerators on ASICs and SoCs. Catapult AI NN starts with a neural network description from an AI framework such as TensorFlow, PyTorch or Keras, converts it into C++ and synthesizes it into an RTL accelerator in Verilog or VHDL for implementation in silicon. Catapult AI NN brings together hls4ml, an open-source package for machine learning hardware acceleration, and Siemens’ Catapult HLS software for High-Level Synthesis. Developed in close collaboration with Fermilab, a U.S. Department of Energy Laboratory, and other leading contributors to hls4ml, Catapult AI NN enables AI experts to develop PPA-optimized accelerators for different applications without requiring them to become ASIC designers.

Read the rest of IP quality assurance; PyTorch-to-RTL; Risc-V growth; new semi subsidies in China; Google’s human brain mapping

The European edition of TSMC’s 2024 Technology Symposium – held in Amsterdam on May 14 – allowed EDACafe to gain some additional insights on the innovations that the Taiwan-headquartered foundry first announced on April 24 at the North America edition of the event. Besides providing a roadmap of new opportunities for chipamkers and OEMs, these innovations also shed some light on the strategies that TSMC is planning to pursue over the next few years to retain its world-leading role.

TSMC’s CEO C.C. Wei on stage in Amsterdam. Credit: TSMC

Entering “the Angstrom era” with the A16 process

Among TSMC’s most notable announcements is the upcoming nanosheet-based A16 process, where A clearly stands for Angstrom. Always keeping in mind what IEEE says about process names (i.e. that today they are just marketing labels, with no connection to the real size of transistor features), it’s inevitable to compare TSMC’s A16 process with Intel’s 18A process, and the difference in numbers – 16 vs 18 – suggests that the Taiwanese foundry hopes to leapfrog competitors even in the Angstrom era. According to the figures released by TSMC, the new A16 process – in comparison to the company’s N2P – will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products. The impact of these achievements can be significant considering large datacenters, where a 20% power reduction translates into a big amount of energy in absolute terms. TSMC’s A16 process is best suited for HPC products and is planned to enter production in 2026. As for moving existing designs to the new process, 86% of standard cells can be ported directly from N2P to A16, whereas 16% need a re-optimization.

Credit: TSMC

Read the rest of Innovations from the 2024 TSMC Technology Symposium

An interesting side effect of the so-called “chip war” is that, now, even large news agencies are sometimes delving quite deep into technology topics. News agency Reuters has recently assigned reverse engineering experts to tear down a Huawei phone, to find out who made the chips inside it. The two companies that performed the analysis – iFixit and TechSearch International – found that Huawei’s Pura 70 Pro contains more China-made parts than previous models, highlighting the progress China is making towards technology self-sufficiency. Chinese components found in the high-end phone include a NAND memory that was likely packaged by Huawei’s in-house chip unit HiSilicon, and a Kirin 9010 processor that is likely a slightly improved version of the chip used by Huawei’s Mate 60 series.

Synopsys to sell its Software Integrity Group

After its recent Ansys acquisition, Synopsys is now focusing on EDA by selling its non-EDA division. The company has entered into a definitive agreement with Clearlake Capital Group and Francisco Partners, two global private equity firms, for the sale of its Software Integrity Group business in a transaction with a total value of up to $2.1 billion. Upon completion of the transaction, the business will emerge as a newly independent application security testing software provider. The existing Software Integrity Group management team is expected to lead the new privately held company, whose name has not been announced yet.

Micron to get $6.1 billion CHIPS Act funding

Micron Technology and the Biden-Harris Administration have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the U.S. CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York. Construction of the new Boise fab – which will be co-located with Micron’s R&D center – started in October 2023. The Idaho fab is expected to come online and be operational in 2025, with DRAM output starting in 2026. In New York, preliminary design, field studies and permitting applications are underway for the project; construction is expected to begin in 2025, with output starting in 2028.

Read the rest of Synopsys to sell Software Integrity Group; Micron to get CHIPS Act funding; 3D solution for RFSOI; recyclable PCBs

EDA-related updates make up most part of this week’s news roundup, with Cadence in particular introducing several new products. But first, a CHIPS Act update.

Samsung to get $6.4 billion under the US CHIPS and Science Act

The U.S. Department of Commerce and Samsung Electronics have signed a non-binding preliminary memorandum of terms to provide up to $6.4 billion in direct funding under the CHIPS and Science Act. Samsung is expected to invest more than $40 billion in the US in the coming years. The proposed investment would turn Samsung’s existing presence in Texas into a comprehensive ecosystem for the development and production of leading-edge chips, including two new leading-edge logic fabs, an R&D fab, and an advanced packaging facility in Taylor, as well as an expansion to their existing Austin facility.

Ansys’ AI-based virtual assistant

Ansys has released its AI-powered virtual assistant, AnsysGPT, built using ChatGPT technology. The virtual assistant provides responses to queries concerning Ansys products, relevant physics, and other complex engineering topics – including simulation setup. AnsysGPT captures knowledge from new public sources, including product documentation, product and engineering-related training documentation, FAQs, technical marketing materials, and public Ansys Learning Forum discussions.

Cadence’s new Palladium and Protium systems

Cadence has announced the new Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, offering more than a 2X increase in capacity and a 1.5X performance increase compared to previous-generation systems. The Palladium Z3 and Protium X3 systems scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models. The new systems are powered by the Nvidia BlueField DPU and Nvidia Quantum InfiniBand networking platforms. Congruency is maintained when transitioning between the two systems and transitioning from virtual to physical interfaces and vice versa. The Palladium Z3 system accelerates hardware verification, and through functional and interface congruency, models can be quickly brought up onto the Protium X3 system for accelerated software validation.

Read the rest of Samsung to receive CHIPS Act funding; AnsysGPT; new Palladium and Protium systems; Cadence’s cloud updates

Unsurprisingly, most news updates this week concern artificial intelligence in one way or another, with several new processor announcements. The so-called chip war is also in the news, with CHIPS Act updates and an analysis about Huawei.

US CHIPS Act updates: TSMC, Applied Materials

US CHIPS and Science Act’s recent updates include some applicant receiving the green-light and others getting a denial, reportedly due to “overwhelming demand”. The U.S. Department of Commerce and TSMC Arizona have signed a non-binding preliminary memorandum of terms to provide up to $6.6 billion to support TSMC’s investment of more than $65 billion in three greenfield leading-edge (2-nanometer) fabs in Phoenix, Arizona. On the other hand, the CHIPS Program Office has announced that it would not move forward with its third Notice of Funding Opportunity to construct, modernize, or expand commercial R&D facilities in the United States at this time. As a consequence, US-headquartered equipment maker Applied Materials may reportedly postpone or abandon its plans to build a $4 billion research and development facility in Silicon Valley.

Datacenter processor update: Google, Meta, Intel

Two hyperscalers have recently announced new homegrown processors. Google has unveiled the Axion Processors family, its first custom Arm-based CPUs designed for the data center. Based on Neoverse V2 CPU, the new devices will be available to Google Cloud customers later this year. According to the company, Axion processors deliver instances with up to 30% better performance than the fastest general-purpose Arm-based instances available in the cloud today, up to 50% better performance and up to 60% better energy-efficiency than comparable current-generation x86-based instances.

Read the rest of TSMC to get CHIPS Act funding; Google’s Arm-based CPU; evolutionary algorithms in AI; Huawei’s growing importance

The news about Intel Foundry takes center stage this week. Prior to summarizing the Intel announcement, here’s a short comment. Before Pat Gelsinger took office as the company’s CEO, some investors suggested Intel to adopt the fabless model, just like AMD in 2008. Gelsinger, instead, doubled down on manufacturing, announcing not just his intention to keep the fabs, but even to offer a foundry service. Intel’s decision to separate the financial reporting for the two parts of its business – foundry service VS chip sales – is probably an unavoidable step in the implementation of Gelsinger’s strategy, and will put it to the test. On the one hand, the new reporting structure will force Intel Products (the chip sales business) to correct its inefficiencies, as it will lose the convenience of easy access to internal manufacturing resources and seemingly costless design respins. On the other hand, Intel Foundry will be forced to quickly become competitive against TSMC, also because – at least officially – Intel Products will now be free to choose any other foundry instead. As of today, an unavoidable side effect of this decoupling is the public disclosure of Intel Foundry’s substantial losses. Will Intel Foundry deliver on its promise of reaching breakeven around 2027? It would be interesting to know if Intel has a plan B, and – if so – if plan B involves going fabless as an extreme option. The new financial reporting structure makes it easy to spot the lossy business within Intel (if any), and this easy spotting capability may sound like setting the stage for divestiture. A key difference from 2008, however, is the current chip war economy, with taxpayers around the world currently subsidizing their respective domestic semiconductor industries. Depending on the dose, public subsidies can offset a company’s inefficiencies and make it competitive on the market. Let’s now move to the Intel announcement and other related news.

Intel’s financial reporting structure to separate Foundry from Products

On April 2, Intel outlined a new financial reporting structure that is aligned with the company’s previously announced foundry operating model. The new reporting structure establishes a foundry relationship between Intel Foundry, the company’s manufacturing organization, and Intel Products, comprised of the company’s product business units. Beginning with the first quarter 2024, Intel will present segment results aligned to the following operating segments: Client Computing Group (CCG); Data Center and AI (DCAI); Network and Edge (NEX); Intel Foundry; Altera; Mobileye; and Other. CCG, DCAI and NEX will collectively be referred to as Intel Products; Altera, Mobileye and Other will collectively be referred to as All Other. Under this new structure, Intel Foundry will recognize revenues generated from both external foundry customers and Intel Products, as well as technology development and product manufacturing costs historically allocated to Intel Products. Instead of recognizing manufacturing costs that were previously allocated to the product operating segments, Intel Products will be charged a market-based price by Intel Foundry. Following the adoption of this new reporting structure, Intel filed a new Form 8-K containing recalculated operating segment results for the years 2023, 2022 and 2021.

Read the rest of New Intel financial reporting structure highlights Intel Foundry’s loss of $7B in 2023

Is pain a positive thing for character-building? Or is it just that humans instinctively need to find a reason to justify pain? Quite an off-topic question here – but not that much, after all, if it stems from a speech given by Nvidia CEO Jensen Huang. For his take on character-building, see the “Further reading” paragraph at the end of this week’s news roundup. But first, some on-topic technology updates.

New Synopsys announcements from SNUG Silicon Valley

Here’s a quick overview of some of the announcements Synopsys made on occasion of its recently held annual Synopsys User Group (SNUG) conference in Silicon Valley. In the area of multi-die designs, 3DSO.ai is a new AI-driven capability built natively into Synopsys 3DIC Compiler, a unified exploration-to-signoff platform. 3DSO.ai offers optimization for signal integrity, thermal integrity, and power-network design. Also targeted at multi-die designs, Synopsys Platform Architect – Multi-Die accelerates design timelines, delivering – according to the company – a six to twelve month “shift left” from RTL for the analysis of performance and power, while accounting for the interdependencies between multiple dies and allowing early partitioning decisions. Synopsys also unveiled two new hardware-assisted verification solutions: ZeBu EP2, the latest version in the ZeBu EP family of unified emulation and prototyping systems; and HAPS-100 12, Synopsys’ highest capacity and density FPGA-based prototyping system. Additionally, the company introduced Synopsys Cloud Hybrid solution, which enables users to burst from on-prem data centers to the cloud during peak needs – automatically splitting the job based on available capacity and eliminating manual data transfers. Lastly, Synopsys announced that it has completed the acquisition of Netherland-headquartered Intrinsic ID, a provider of Physical Unclonable Function (PUF) IP.

Altair to extend its meshless technology to electronics

Altair has announced the upcoming release of Altair SimSolid for electronics – promising fast, easy, and precise multi-physics scenario exploration for electronics, from chips to PCBs and full system design. SimSolid is an already existing Altair product, which so far has gained adoption in industries such as aerospace and automotive. According to the company, SimSolid’s main benefit is its ability to eliminate geometry simplification and meshing, the two most time-consuming and expertise-intensive tasks done in traditional finite element analysis. As a result, it is up to 25x faster than traditional finite element solvers, and effortlessly handles complex assemblies. Extending Altair SimSolid’s meshless technology to electronics will enable the tool to tackle intricate challenges like signal integrity, power integrity, and electromagnetic compatibility/interference, all while making simulations more accessible and efficient.

Read the rest of SNUG announcements; meshless multiphysics simulation; flaws in AI-generated RTL; open-source alternative to CUDA; skyrmion-based memory

Not just GPU-based acceleration: the partnerships announced on occasion of this year’s GTC event demonstrate that Nvidia software, too, is a key technology in several existing or upcoming EDA tools

EDA and engineering software received quite a bit of attention at the recent Nvidia GTC event, with “rockstar” CEO Jensen Huang mentioning this theme during his two-hour long keynote, and with some of the major vendors (namely Ansys, Cadence, Siemens – the German parent company, not Mentor – and Synopsys) issuing GTC-related press releases to announce their extended collaboration with Nvidia. While partnerships between Nvidia and EDA vendors are not new, this level of emphasis from both sides seems unprecedented and deserves a closer look.

The announcements issued by EDA and engineering software vendors highlight three main areas of collaboration with Nvidia: GPU-based acceleration; Omniverse-based visualization; and the use of AI development tools encompassed by the Nvidia “AI Foundry” offering. A fourth area, the only one specifically related to the EDA flow, is optical proximity correction based on Nvidia cuLitho.

Software acceleration based on Nvidia GPUs

In GTC-related announcements, the use of Nvidia GPUs for software acceleration was highlighted by Ansys, Cadence and Synopsys. Ansys harnesses Nvidia H100 Tensor Core GPUs to boost multiple simulation solutions, and prioritizes the new Nvidia Blackwell-based processors and Nvidia Grace Hopper for products across its portfolio – including Ansys Fluent, Ansys LS-Dyna, and its electronics and semiconductor products. As for Cadence, previously announced collaborations with Nvidia include the GPU-optimized Fidelity CFD (computational fluid dynamics) software and the Millennium Enterprise Multiphysics Platform, a hardware box for the acceleration of CFD simulations based on Nvidia GPUs. Synopsys is applying Nvidia accelerated compute architectures, including the GH200 Grace Hopper, across its full EDA stack spanning design, verification, simulation and manufacturing. The tool list includes Synopsys VCS, Synopsys Fusion Compiler, Synopsys PrimeSim, Synopsys Proteus (see below).

Read the rest of Nvidia’s role in the EDA industry

Will “programmed logic” (that is, GPUs and deep learning accelerators) give way to “hard-wired logic” in artificial intelligence applications? Taalas, a startup recently emerged from stealth, has no doubt about that (see the news below). Meanwhile, programmed logic keeps advancing – with Cerebras doubling down on its wafer-scale approach and launching a four trillion transistor chip. Other news this week, besides Taalas, contribute to the feeling that the end of geometrical scaling won’t stop IT advancements. That includes chiplet-based solutions, of course, but also new transistor types.

Hard-wired AI models promise a 1000x improvement in computational power and efficiency

Toronto-based Taalas has recently exited stealth mode and raised $50 million dollars over two rounds of funding led by Pierre Lamond and Quiet Capital. The company’s mission is to develop an automated flow for rapidly implementing all types of deep learning models (transformers, SSMs, diffusers, MoEs, etc.) in silicon. According to the company, proprietary innovations enable one of its chips to hold an entire large AI model without requiring external memory. Taalas claims that the efficiency of hard-wired computation enables a single chip to outperform a small GPU-based data center, opening the way to a 1000x improvement in the cost of AI. “The path forward is to realize that we should not be simulating intelligence on general purpose computers, but casting intelligence directly into silicon. Implementing deep learning models in silicon is the straightest path to sustainable AI,” said Ljubisa Bajic, Taalas’ CEO. Prior to co-founding Taalas, Bajic founded Tenstorrent in 2016.

Intel outlines a UCIe-3D solution

In a paper recently published on Nature Electronics, a team of Intel researchers propose a solution for using the UCIe standard in the three-dimensional integration of chiplets. According to the authors, their architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm. Research findings include that – contrary to trends seen in traditional signalling interfaces – the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. The Intel vision is that two chiplets will connect using multiple independent modules, with each UCIe-3D PHY directly controlled by the Network-on-Chip controller. To realize this vision, the authors anticipate challenges in the areas of cooling, power delivery and reliability. Advances in electronic design automation will be necessary, too.

Read the rest of Hard-wired AI models; UCIe in 3D packages; reconfigurable FETs; Samsung’s HBM3; Silicon Box in Italy

The U.S. government is reportedly asking the Netherlands, Germany, South Korea and Japan to put in place additional restrictions on exports to China. Japan is being asked to limit exports of chemicals such as photoresist, the Netherlands to stop ASML from servicing and repairing lithography equipment installed in China before limits on sales were put in place. Moving to this week’s news roundup, the trend towards convergence between EDA and the rest of engineering software continues – with Cadence’s acquisition of Beta CAE. Even though much smaller in financial terms ($1.24 billion), this move can be likened to the recent Synopsys’ acquisition of Ansys.

Cadence acquires structural analysis tool vendor Beta CAE

Cadence has entered into a definitive agreement to acquire Switzerland-based Beta CAE, a leading provider of structural analysis and multi-domain simulation solutions. Beta CAE has a strong presence in the automotive industry. Its flagship products include Ansa, a multidisciplinary CAE pre-processor, and Meta, a multidisciplinary CAE post-processor. Additionally, Beta CAE’s Epilysis and Fatiq solvers are used in structural analysis and optimization problems, while the SPDRM (simulation, process, data, and resources management) tool manages the CAE processes. According to Cadence, Beta CAE’s products are very complementary to Cadence’s multiphysics system analysis portfolio – which includes Clarity, Celsius, Sigrity, Voltus, Fidelity and the recently announced Millennium M1 multiphysics platform.

Altera gets its name back after eight years

Following last October decision to operate its Programmable Solutions Group as a standalone business, Intel has recently rebranded it as “Altera”. In other words, the entity is getting its original name back. Intel bought FPGA vendor Altera in 2015 and dropped its name. Now this famous brand will reappear, with the addition of “An Intel Company”. Led by CEO Sandra Rivera, Altera is now seeking additional growth opportunities in AI applications. The company has preannounced a new product series called Agilex 3 – a low-power line of FPGAs aimed at low-complexity functions for cloud, communications and intelligent edge applications. Intel plans to hold a public offering for stock in Altera over the next two to three years.

Read the rest of Cadence acquires Beta CAE; Altera gets its name back; EDA standard updates; ChatGPT-generated Verilog code