Arm’s Initial Public Offering is proving successful: share price increased almost 25% soon after the company’s Nasdaq listing, which translates into a $65 billion valuation. More themes this week include memory tiering in the datacenters and a new way to use AI in chip design.
AI-enhanced, cloud-based PCB design
The AI-in-EDA trend extends to PCB tools. The new Cadence OrCAD X Platform promises up to 5X faster PCB design thanks to generative AI automation to reduce placement time, and by leveraging Cadence OnCloud integration. According to Cadence, the solution is optimized for small and medium businesses, offering a new, easy-to-learn and easy-to-use PCB layout canvas.
New MLPerf benchmarks
MLPerf Inference v3.1 introduces two new benchmarks to the suite. The first is a large language model (LLM) using the GPT-J reference model to summarize CNN news articles. The second is an updated recommender, modified to be more representative of industry practices, using the DLRM-DCNv2 reference model and a much larger dataset. The latest MLPerf results also include, for the first time, the MLPerf Storage benchmark, which measures the performance of storage systems in the context of ML training workloads.
The Chinese government will reportedly launch an additional state-backed investment fund aiming to raise about $40 billion for the domestic semiconductor industry. According to Reuters, individual Chinese chipmakers that have already received state subsidies include GTA Semiconductor, specializing in automotive applications, which was reportedly granted over $1.8 billion. Other updates related to the US-China tensions include the growing capability of Chinese chipmakers: more than half, maybe two-thirds of the chips contained in Huawei’s new high-end smartphone are made in China, according to Canadian reverse engineering firm TechInsights. Lastly, the Chinese government has reportedly told state employees to stop using their iPhones at work.
Synopsys unveils its big data analytics solution
Synopsys has extended its Synopsys.ai full-stack EDA suite with a comprehensive AI-driven data analytics continuum for every stage of chip development, leveraging the vast amounts of heterogeneous design data generated by EDA, testing, and IC fabrication tools – such as timing paths, power profiles, die pass/fail reports, process control, or verification coverage metrics. The AI-driven Synopsys EDA Data Analytics (.da) solution includes: Synopsys Design.da to perform deep analysis of data, to uncover PPA opportunities; Synopsys Fab.da to store and analyze large streams of fab equipment process control data, to maximize product quality and fab yield; Synopsys Silicon.da to collect petabytes of silicon monitor, diagnostic, and production test data from test equipment, to improve chip production metrics.
Catching up on some of the news from the last thirty days or so, let’s start with the upcoming change of Synopsys’ top management: on January 1st 2024, Sassine Ghaziwill replace Aart de Geus as Synopsys’ Chief Executive Officer. Ghazi assumed the role of Synopsys COO in August 2020 and was appointed to the role of president in November 2021. De Geus (69), founded Synopsys in 1986.
Arm to go public
As previously announced, Arm is going public. On August 20, the company announced that it has publicly filed a registration statement with the U.S. Securities and Exchange Commission relating to its initial public offering on the Nasdaq Global Select Market under the symbol “ARM”.
Nvidia Q2 record results
Nvidia reported record results for the second quarter ended July 30, 2023: global revenue was $13.51 billion, up 88% from Q1 and up 101% from year ago; Data Center revenue was $10.32 billion, up 141% from Q1 and up 171% from year ago. Nvidia has also announced an expanded partnership with Google Cloud which will include the general availability of purpose-built Google Cloud A3 virtual machines powered by Nvidia H100 GPUs.
Recent announcements from Ansys include the introduction of its latest release, 2023 R2, and the limited beta release of AnsysGPT, a multilingual, conversational, AI virtual assistant for customer support. Developed using ChatGPT technology available via the Microsoft Azure OpenAI Service, AnsysGPT uses Ansys public data to answer technical questions concerning Ansys products, relevant physics, and engineering topics. Another recent announcement from the company concerns the digital connection of Altium’s electronic computer-aided design tools and Ansys simulation tools included in Ansys Electronics Desktop.
Cadence’s Joules RTL Design Studio
Cadence has announced its Joules RTL Design Studio, a new solution to accelerate the RTL design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, which – according to the company – will enable fully optimized RTL design prior to implementation handoff. Users will also be able to leverage generative AI for RTL design exploration and big data analytics. According to Cadence, by enabling quick and accurate physical estimates, Joules RTL Design Studio can unlock up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.
Artificial intelligence, Moore’s law, chiplets, and High NA EUV were among the themes discussed by keynoters and panelists at the two industry events, both held in San Francisco from July 9-10 to July 13
Thousands of industry professionals and academic researchers involved in all different aspects of the semiconductor ecosystem gathered in San Francisco last week – either as attendees, exhibitors, presenters, or speakers – for the 2023 editions of the Design Automation Conference and Semicon West. Back to normal after the pandemic, the two co-located events offered a rich menu to the semiconductor community – combining research papers, exhibition floors, keynotes and panels. Adding to this offering, Semicon West was also co-located with the Flex event, and two European semiconductor research institutes – Belgium’s imec and France’s CEA-Leti – also organized their own forums at venues nearby (ITF Semicon USA and Leti Semicon Workshop, respectively). Here we will try to summarize some of the concepts that emerged from some of the keynotes and panels.
EDA: no disruptions ahead
Let’s start with EDA. Overall, it looks like the industry is not expecting any major disruptions on the short term. Artificial intelligence will obviously continue to play a key role in the evolution of EDA tools, but today this can be taken for granted and cannot be considered a new trend anymore. Part of the debate about EDA concerned the adaptation of existing EDA tools to the change of external conditions, such as the advent of cloud computing. The lack of disruptive innovations was effectively summarized by a rather provocative questions asked by Prit Banerjee, Ansys’ CTO, to EDA veterans Joe Costello and Wally Rhines during a panel. In short, Banerjee – speaking from the audience, not as a panelist – maintained that until now the major EDA vendors have just “tweaked” their EDA tools to adapt them to new technologies – such as parallel processing, AI, cloud computing – and asked if there is now space for a new EDA flow that is natively optimized for those new resources. Joe Costello answered that it’s a great idea, but today it would be difficult to find the money to undertake such an effort.
Reportedly, the latest update on the U.S.-China tech fight is China’s decision to place exports restriction on gallium and germanium, which – according to some observers – could be followed by restrictions on rare earth exports. As for semiconductor subsidies updates, Broadcom will reportedly invest in a European Union-funded program in Spain which would include the construction of “large-scale back-end semiconductors facilities unique in Europe.” And French research institute CEAwill receive funding from the French government for the construction of a new fab in Grenoble with the goal of downscaling FD-SOI (fully depleted silicon on insulator) chips below 10-nanometer and a to develop a new generation non-volatile onboard memory.
Samsung Foundry roadmap updates
On occasion of its recent Samsung Foundry Forum in San Jose, the South Korean company announced it will begin mass production of the 2-nanometer process for mobile applications in 2025, and then expand to HPC in 2026 and automotive in 2027. Mass production of SF1.4 will begin in 2027 as planned. From 2025, Samsung will begin foundry services for 8-inch gallium nitride power semiconductors. The 5-nanometer radio frequency process is also under development and will be available in the first half of 2025. Samsung Foundry is adding new manufacturing lines in Pyeongtaek, South Korea, and Taylor, Texas. The company said the construction of the new fab in Taylor is proceeding according to initial plans and is expected to finish by the end of the year, beginning operation in the second half of 2024. Among other news, Samsung is launching its ‘Multi-Die Integration Alliance’ in collaboration with partner companies and players in memory, substrate packaging, and testing. The MDI Alliance aims to create a packaging technology ecosystem for 2.5D and 3D heterogeneous integration.
A fund backed by the Japanese government has reportedly agreed to buy Japanese photoresists supplier JSR. The deal would represent an additional effort of the Japanese government to revitalize its domestic semiconductor industry. Among the other interesting news this week, Intel implicitly admitting (in this press release) that it is currently spending up to $1.5 billion per year due to operational inefficiencies that its competitors don’t have. This refers to expedited wafers and test times, as explained below.
Intel to adopt an internal “fabless-foundry” model
Intel will adopt a new operating model where its internal product groups will move to a foundry-style relationship with the company’s manufacturing group. In this new “internal foundry” model, Intel’s product business units will engage with the company’s manufacturing group in a similar fashion that fabless semiconductor companies engage with external foundries. Intel’s manufacturing groups will be accountable to a standalone profit and loss (P&L) for the first time. The company expects this change to boost efficiency and therefore deliver significant cost savings. One example concerns “expedited” wafers that business units decide to move through Intel’s manufacturing process, which are costly and reduce factory efficiency. Going forward, this service charge will be borne by the business units, and it’s expected that it will reduce the number of expedites “to be on par with the competition”. Another example concerns Intel’s test times, which currently run “double or triple those of competitors”. As business units are charged market prices based on test time, Intel expects pre-silicon design choices to reduce these test times.
In view of its upcoming IPO, Arm is reportedly looking for some “anchor investors” among its main customers and end users. Companies in talks with Arm include Intel, Alphabet, Apple, Microsoft, TSMC, and Samsung. Let’s now move to this week’s news roundup, which mostly concerns EDA and IP. Among the other news, AMD disclosing details about its artificial intelligence products and strategy.
RF EDA updates: Keysight, Xpeedic
Keysight has introduced a new release of its PathWave Advanced Design System. The ADS 2024 suite offers new millimeter wave and subterahertz frequency capabilities targeting 5G and future 6G chips. According to Keysight, 3D electromagnetic analysis can be accelerated thanks to next-generation solvers, application-aware meshing algorithms, and an innovative circuit co-design and simulation approach. Increased circuit designer productivity is achieved through enhancements to the RFPro tool, which streamlines monolithic microwave integrated circuit and module workflows. Performance for microwave power amplifier designs can also be improved thanks to electrothermal simulation, signal modulation, and analysis capabilities. Xpeedic, too, has recently unveiled a new edition of its RF EDA solution. Innovations concern XDS, Xpeedic’s RF system-level design and simulation platform; IRIS, its on-chip passive modeling and simulation tool; and iModeler, a passive model generation tool.
Updates concerning automotive applications make up a significant part of this week’s news roundup. Among the other themes, backside power delivery is getting closer to real-life applications; and more subsidies are going to benefit the European semiconductor ecosystem.
More European subsidies
In addition to the EU Chips Act, the European Union and some individual member States are going to provide more subsidies to their domestic semiconductor ecosystem. The European Commission has approved an “Important Project of Common European Interest” (‘IPCEI’) to support research, innovation and the first industrial deployment of microelectronics and communication technologies across the value chain. Fourteen member States will provide up to €8.1 billion in public funding, which is expected to unlock additional €13.7 billion in private investments. As part of this IPCEI, 56 companies, including small and medium-sized enterprises and start-ups, will undertake 68 projects.
Source: European Commission
Separately, the French government has announced it will provide 2.9 billion euros ($3.10 billion) in state aid to help support an investment of 7.5 billion euros that STMicroelectronics and GlobalFoundries are making to build a semiconductor factory in Crolles, France.
Open-source software for an open-source ISA: the Risc-V Software Ecosystem (RISE) Project is a new initiative dedicated to enabling a software ecosystem for application processors that includes software development tools, virtualization support, language runtimes, Linux distribution integration, and system firmware, working upstream first with existing open-source communities in accordance with open-source best practices. The RISE Governing Board includes Andes, Google, Intel, Imagination, MediaTek, Nvidia, Qualcomm, Red Hat, Rivos, Samsung, SiFive, T-Head, and Ventana.
New Arm mobile computing platform
At the recent Computex event in Taiwan, Arm announced its Total Compute Solutions 2023 (TCS23), a new platform for mobile computing aimed at premium smartphones. TCS23 IP includes a new Arm Immortalis GPU based on the 5th Generation GPU architecture, a new cluster of Armv9 CPUs supporting artificial intelligence, and other enhancements. A new graphics feature introduced in the 5th Gen GPU architecture is Deferred Vertex Shading (DVS), a technique that redefines the dataflow and enables partners to scale for larger core counts and higher performance points. A key part of the CPU cluster is the new Arm Cortex-X4 – “the fastest CPU that we have ever built,” Arm stated in a blog post – bringing 15 percent more performance compared to the Cortex-X3 while consuming 40 percent less power on the same process. Arm is taping out the Cortex-X4 on the TSMC N3E process.
Cadencewill support customers using the new Arm TCS23 through RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) for 3nm and 5nm nodes. The company has fine-tuned its RAKs for Arm Cortex-X4, Cortex-A720 and Cortex-A520 CPUs and Immortalis-G720, Mali-G720 and Mali-G620 GPUs. Cadence verification flow has also been optimized for the newest Arm CPUs and GPUs.
Synopsys, too, has announced support for TCS23 through QuickStart Implementation Kits (QIKs) that are tuned for the latest 5, 4 and 3nm process technologies.
