Catching up on some of the news from the last twenty-five days or so, this week we report about some interesting EDA related updates – but first, some press reports and company announcements suggesting an upcoming shakeup in the PC processor landscape.

Nvidia to reportedly develop Arm-based processors for Windows PCs

According to a Reuters report, Nvidia has begun designing Arm-based CPUs that would run Microsoft Windows. Nvidia’s initiative is reportedly driven by Microsoft’s effort to help chipmakers build Arm-based processors for Windows PCs, trying to replicate the success that Apple is having with its own Arm-based chips for Mac computers. Qualcomm has been making Arm-based chips for Windows laptops since 2016, but its exclusive license is reportedly expiring in 2024. After that deadline, Microsoft would encourage more chipmakers to join the effort, to avoid relying solely on Qualcomm. AMD is also reportedly planning to make chips for PCs with Arm technology.

Qualcomm’s new PC processor

And Qualcomm has just unveiled the Snapdragon X Elite platform for PCs. It features the custom integrated Qualcomm Oryon CPU and – according to the company – delivers up to two times faster CPU performance versus the competition, matching competitor peak performance with one-third of the power. In terms of AI performance, Qualcomm claims that Snapdragon X Elite can run generative AI models with over 13 billion parameters on-device. PCs powered by Snapdragon X Elite are expected starting mid-2024.

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OpenAI, the company behind ChatGPT, is reportedly exploring making its own artificial intelligence chips, possibly through the acquisition of an AI chip company. According to a Reuters report, OpenAI aims to gain independence from expensive Nvidia GPUs.

New EDA releases: Keysight, Nullspace, Mathworks

Keysight EDA 2024 software suite offers three major “shift left” updates. “RF System Explorer” streamlines system and circuit level design workflows for early exploration of system architectures in Advanced Design System; “Digital Pre-Distortion Explorer” and “Digital Pre-Distortion Designer” accelerate wide bandgap power amplifier design and validation using the Dynamic Gain Model; “SystemVue” delivers complete Satcom modeling and simulation solutions for 5G non-terrestrial network, DVB-S2X, and phased array product development.

Nullspace has launched the Nullspace Prep and Nullspace EM 2023.9 release, claiming a 2-4x simulation speed improvement for large problems. The company is also releasing the Nullspace EM Solver on the Windows platform; up until now, the product was only available on Linux. Users interested in the Windows version can apply to take part in a Beta program. Additionally, Nullspace has authored a new whitepaper, “Overcoming Limitations of 3D EM Simulation of Electrically Large Devices.”

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Will Silicon Valley’s disruptive innovation capabilities extend to car body manufacturing? In addition to pioneering the use of huge presses with 6,000 to 9,000 tons of clamping pressure, Tesla is reportedly exploring other new solutions to slash the cost of electric vehicles. Technologies being investigated include 3D printing, industrial sand, tailor-made alloys. According to the report, Musk’s goal is to find a way to cast the car’s underbody in one piece.

EDA and IP updates: Zuken, Altair, Ultra Librarian, Intel

Zuken has introduced a three-stage approach to AI-powered PCB design within its CR-8000 platform. The Autonomous Intelligent Place and Route product line introduces a new platform for AI-based place and route, which evolves in stages. “Basic Brain” learns from Zuken’s library of design examples and existing design expertise, and routes the design utilizing the product’s Smart Autorouter based on learned approaches and strategies. In the second stage, Zuken’s “Dynamic Brain” learns from the customer’s PCB designers, utilizing past design examples and integrating them into AI algorithms. The third and final stage is the “Autonomous Brain”, an AI-driven capability that self-improves with each project.

The Ultra Librarian CAD model library is now available to Altair users in several Altair ECAD verification and multiphysics solutions, including PollEx, SimLab, and Altair One UDE. Ultra Librarian gives users instant access to more than 16 million symbols, footprints from a cloud-based library.

And Ultra Librarian has developed a new AI-driven CAD modeling engine to drastically reduce the time it takes to build CAD models.

Intel is launching a new soft processor in the Nios V family targeting its FPGAs: the Nios V/c compact microcontroller – a free, soft-core IP, based on the Risc-V architecture. It will initially target all devices supported in Intel Quartus Prime Pro software with a roadmap to many devices supported in Quartus Prime Standard software.

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Arm’s Initial Public Offering is proving successful: share price increased almost 25% soon after the company’s Nasdaq listing, which translates into a $65 billion valuation. More themes this week include memory tiering in the datacenters and a new way to use AI in chip design.

AI-enhanced, cloud-based PCB design

The AI-in-EDA trend extends to PCB tools. The new Cadence OrCAD X Platform promises up to 5X faster PCB design thanks to generative AI automation to reduce placement time, and by leveraging Cadence OnCloud integration. According to Cadence, the solution is optimized for small and medium businesses, offering a new, easy-to-learn and easy-to-use PCB layout canvas.

New MLPerf benchmarks

MLPerf Inference v3.1 introduces two new benchmarks to the suite. The first is a large language model (LLM) using the GPT-J reference model to summarize CNN news articles. The second is an updated recommender, modified to be more representative of industry practices, using the DLRM-DCNv2 reference model and a much larger dataset. The latest MLPerf results also include, for the first time, the MLPerf Storage benchmark, which measures the performance of storage systems in the context of ML training workloads.

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The Chinese government will reportedly launch an additional state-backed investment fund aiming to raise about $40 billion for the domestic semiconductor industry. According to Reuters, individual Chinese chipmakers that have already received state subsidies include GTA Semiconductor, specializing in automotive applications, which was reportedly granted over $1.8 billion. Other updates related to the US-China tensions include the growing capability of Chinese chipmakers: more than half, maybe two-thirds of the chips contained in Huawei’s new high-end smartphone are made in China, according to Canadian reverse engineering firm TechInsights. Lastly, the Chinese government has reportedly told state employees to stop using their iPhones at work.

Synopsys unveils its big data analytics solution

Synopsys has extended its Synopsys.ai full-stack EDA suite with a comprehensive AI-driven data analytics continuum for every stage of chip development, leveraging the vast amounts of heterogeneous design data generated by EDA, testing, and IC fabrication tools – such as timing paths, power profiles, die pass/fail reports, process control, or verification coverage metrics. The AI-driven Synopsys EDA Data Analytics (.da) solution includes: Synopsys Design.da to perform deep analysis of data, to uncover PPA opportunities; Synopsys Fab.da to store and analyze large streams of fab equipment process control data, to maximize product quality and fab yield; Synopsys Silicon.da to collect petabytes of silicon monitor, diagnostic, and production test data from test equipment, to improve chip production metrics.

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Catching up on some of the news from the last thirty days or so, let’s start with the upcoming change of Synopsys’ top management: on January 1^st 2024, Sassine Ghazi will replace Aart de Geus as Synopsys’ Chief Executive Officer. Ghazi assumed the role of Synopsys COO in August 2020 and was appointed to the role of president in November 2021. De Geus (69), founded Synopsys in 1986.

Arm to go public

As previously announced, Arm is going public. On August 20, the company announced that it has publicly filed a registration statement with the U.S. Securities and Exchange Commission relating to its initial public offering on the Nasdaq Global Select Market under the symbol “ARM”.

Nvidia Q2 record results

Nvidia reported record results for the second quarter ended July 30, 2023: global revenue was $13.51 billion, up 88% from Q1 and up 101% from year ago; Data Center revenue was $10.32 billion, up 141% from Q1 and up 171% from year ago. Nvidia has also announced an expanded partnership with Google Cloud which will include the general availability of purpose-built Google Cloud A3 virtual machines powered by Nvidia H100 GPUs.

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Catching up on some of the news from the last thirty days or so, this week we will focus on some of the latest EDA announcements.

Ansys’ 2023 R2 release, AnsysGPT, Ansys-Altium connection

Recent announcements from Ansys include the introduction of its latest release, 2023 R2, and the limited beta release of AnsysGPT, a multilingual, conversational, AI virtual assistant for customer support. Developed using ChatGPT technology available via the Microsoft Azure OpenAI Service, AnsysGPT uses Ansys public data to answer technical questions concerning Ansys products, relevant physics, and engineering topics. Another recent announcement from the company concerns the digital connection of Altium’s electronic computer-aided design tools and Ansys simulation tools included in Ansys Electronics Desktop.

Cadence’s Joules RTL Design Studio

Cadence has announced its Joules RTL Design Studio, a new solution to accelerate the RTL design and implementation process. Front-end designers can access digital design analysis and debugging capabilities from a single, unified cockpit, which – according to the company – will enable fully optimized RTL design prior to implementation handoff. Users will also be able to leverage generative AI for RTL design exploration and big data analytics. According to Cadence, by enabling quick and accurate physical estimates, Joules RTL Design Studio can unlock up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.

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Artificial intelligence, Moore’s law, chiplets, and High NA EUV were among the themes discussed by keynoters and panelists at the two industry events, both held in San Francisco from July 9-10 to July 13

Thousands of industry professionals and academic researchers involved in all different aspects of the semiconductor ecosystem gathered in San Francisco last week – either as attendees, exhibitors, presenters, or speakers – for the 2023 editions of the Design Automation Conference and Semicon West. Back to normal after the pandemic, the two co-located events offered a rich menu to the semiconductor community – combining research papers, exhibition floors, keynotes and panels. Adding to this offering, Semicon West was also co-located with the Flex event, and two European semiconductor research institutes – Belgium’s imec and France’s CEA-Leti – also organized their own forums at venues nearby (ITF Semicon USA and Leti Semicon Workshop, respectively). Here we will try to summarize some of the concepts that emerged from some of the keynotes and panels.

EDA: no disruptions ahead

Let’s start with EDA. Overall, it looks like the industry is not expecting any major disruptions on the short term. Artificial intelligence will obviously continue to play a key role in the evolution of EDA tools, but today this can be taken for granted and cannot be considered a new trend anymore. Part of the debate about EDA concerned the adaptation of existing EDA tools to the change of external conditions, such as the advent of cloud computing. The lack of disruptive innovations was effectively summarized by a rather provocative questions asked by Prit Banerjee, Ansys’ CTO, to EDA veterans Joe Costello and Wally Rhines during a panel. In short, Banerjee – speaking from the audience, not as a panelist – maintained that until now the major EDA vendors have just “tweaked” their EDA tools to adapt them to new technologies – such as parallel processing, AI, cloud computing – and asked if there is now space for a new EDA flow that is natively optimized for those new resources. Joe Costello answered that it’s a great idea, but today it would be difficult to find the money to undertake such an effort.

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Reportedly, the latest update on the U.S.-China tech fight is China’s decision to place exports restriction on gallium and germanium, which – according to some observers – could be followed by restrictions on rare earth exports. As for semiconductor subsidies updates, Broadcom will reportedly invest in a European Union-funded program in Spain which would include the construction of “large-scale back-end semiconductors facilities unique in Europe.” And French research institute CEA will receive funding from the French government for the construction of a new fab in Grenoble with the goal of downscaling FD-SOI (fully depleted silicon on insulator) chips below 10-nanometer and a to develop a new generation non-volatile onboard memory.

Samsung Foundry roadmap updates

On occasion of its recent Samsung Foundry Forum in San Jose, the South Korean company announced it will begin mass production of the 2-nanometer process for mobile applications in 2025, and then expand to HPC in 2026 and automotive in 2027. Mass production of SF1.4 will begin in 2027 as planned. From 2025, Samsung will begin foundry services for 8-inch gallium nitride power semiconductors. The 5-nanometer radio frequency process is also under development and will be available in the first half of 2025. Samsung Foundry is adding new manufacturing lines in Pyeongtaek, South Korea, and Taylor, Texas. The company said the construction of the new fab in Taylor is proceeding according to initial plans and is expected to finish by the end of the year, beginning operation in the second half of 2024. Among other news, Samsung is launching its ‘Multi-Die Integration Alliance’ in collaboration with partner companies and players in memory, substrate packaging, and testing. The MDI Alliance aims to create a packaging technology ecosystem for 2.5D and 3D heterogeneous integration.

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A fund backed by the Japanese government has reportedly agreed to buy Japanese photoresists supplier JSR. The deal would represent an additional effort of the Japanese government to revitalize its domestic semiconductor industry. Among the other interesting news this week, Intel implicitly admitting (in this press release) that it is currently spending up to $1.5 billion per year due to operational inefficiencies that its competitors don’t have. This refers to expedited wafers and test times, as explained below.

Intel to adopt an internal “fabless-foundry” model

Intel will adopt a new operating model where its internal product groups will move to a foundry-style relationship with the company’s manufacturing group. In this new “internal foundry” model, Intel’s product business units will engage with the company’s manufacturing group in a similar fashion that fabless semiconductor companies engage with external foundries. Intel’s manufacturing groups will be accountable to a standalone profit and loss (P&L) for the first time. The company expects this change to boost efficiency and therefore deliver significant cost savings. One example concerns “expedited” wafers that business units decide to move through Intel’s manufacturing process, which are costly and reduce factory efficiency. Going forward, this service charge will be borne by the business units, and it’s expected that it will reduce the number of expedites “to be on par with the competition”. Another example concerns Intel’s test times, which currently run “double or triple those of competitors”. As business units are charged market prices based on test time, Intel expects pre-silicon design choices to reduce these test times.

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