A closer look at the new solution with the help of Rob Knoth, Product Management Group Director in the Digital & Signoff Group at Cadence

With its recently announced “Joules RTL Design Studio”, Cadence is offering “a new solution that provides users with actionable intelligence to accelerate the register transfer level (RTL) design and implementation process.” According to Cadence, front-end designers can now access digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff. For years, Cadence maintains, front-end designers have lacked visibility of RTL metrics on power, performance, area, and congestion (PPAC). Now, with the Joules RTL Design Studio, exploration and prototyping are possible prior to committing the design to the place and route phase.

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Flagship product of the new engineering software company – a spinoff from defense contractor IERUS Technologies – is an electromagnetic simulation software that has been tested on real-world antenna, microwave, and scattering problems for the last twelve years

Wireless applications are getting ever more complex in several key industries such as defense, aerospace, 5G/6G communications, and automotive. Some of the design challenges concern multi- and wideband antennas, active and passive electronically steered arrays, MIMO antennas with complex beamforming, complex microwave networks, cosite interference when multiple antennas are placed on vehicles or aircrafts, and more. Companies developing advanced communication systems rely on electromagnetic simulation software that must combine speed, accuracy and flexibility, to reduce the development time while avoiding design errors.

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A closer look at the recently announced ‘Joint Enterprise Data and AI’ infrastructure, an AI-driven, big data analytics environment

Announced last September 13, the JedAI platform is the new Cadence AI-driven, big data analytics environment, meant to be tightly integrated with the company’s recently introduced AI-based platforms: Verisium for verification, Cerebrus for implementation, and Optimality for system optimization. Features and benefits of JedAI were described by Rod Metcalfe – Product Management Group Director, Digital and Signoff Group at Cadence – in the video interview he recently gave to EDACafe’s Sanjay Gangal; building on that interview, in this article we will add a few more details with the help of a Cadence white paper – along with the answers provided by Rod and by Kam Kittrell – vice president, Product Management in the Digital & Signoff Group at Cadence – to some additional questions.

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Thanks to real-time integration with the physical design flow and to new optimization algorithms, the solution promises dramatic TAT improvements and significant PPA benefits for large SoCs and multi-die designs – running on single box hardware

Major EDA vendors are launching new products to address the challenges of design closure and ECOs in deep-submicron SoCs. On October 5^th Synopsys introduced its new PrimeClosure solution. Jacob Avidan, senior vice president of Engineering for the Silicon Realization Group at Synopsys, described the features of PrimeClosure in the video interview he recently gave to EDACafe’s Sanjay Gangal. Building on that interview, in this article we will add some more details about the new solution by means of the answers that Manoj Chacko, Director of Product Marketing for Synopsys PrimeClosure, provided to our additional questions.

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Based on a parallel architecture and a ‘distributed optimization engine’, the new automated environment builds on Cadence’s implementation system (Innovus) and timing signoff solution (Tempus), and promises up to 10X faster closure for designs greater than ten million cells

With SoCs targeted at advanced applications getting ever larger and complex, moving from block-level optimization to full-chip design closure has become a challenging and time-consuming task for design teams. The current, manual full-chip closure flow involves many steps and iterations – from assembly, static timing analysis, and optimization and signoff with hundreds of views. According to Cadence, today’s design teams often spend five to seven days per iteration to meet chip-level signoff timing and power requirements, therefore this error-prone process can take designers months to converge.

Additionally, current methodologies are considered inefficient in terms of team collaboration and user experience. Addressing these problems, Cadence has recently launched Certus Closure Solution, an environment aimed at accelerating full-chip design closure by means of a parallel architecture and automation of previously manual tasks. Brandon Bautz – Senior Group Director of Product Management, responsible for the Cadence silicon signoff and verification product lines in the Digital & Signoff Group at Cadence – described the features of Certus in the video interview he recently gave to EDACafe’s Sanjay Gangal. In this article we will add some more details about Certus, building on that video interview and on the answers Bautz provided to our additional questions.

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A closer look at the new platform – currently focused on debugging – with the help of Cadence’s Matt Graham

With ever-growing device size and complexity, SoC verification has become an extremely challenging task, often requiring more compute time and qualified human resources than any other step in the engineering flow. According to a Cadence estimate, the verification effort can often climb to more than 500 years of compute time – with tens of millions of runs and hundreds of millions of coverage bins, to uncover thousands of bugs. Debugging alone can consume multiple weeks of time of many engineers. In terms of time-to-market, therefore, verification can be considered a key limiting factor and a potential cause of schedule slips. Reconciling a thorough verification coverage with a tight SoC development schedule clearly calls for better productivity through automation, an even more challenging goal. A new approach to improving verification productivity is now proposed by Cadence with its Verisium Artificial Intelligence-Driven Verification Platform – a suite of applications leveraging big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs. The Verisium platform is built on the new Cadence Joint Enterprise Data and AI (JedAI) Platform and is natively integrated with the Cadence verification engines. The initial suite of apps available in the Verisium platform is focused on debugging, a very significant part of verification. Matt Graham, group director at Cadence Design Systems, described the Verisium apps in the video interview he recently gave to EDACafe’s Sanjay Gangal; in this article we will summarize his answers and add a few details, as well as the responses he provided to some additional questions.

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Saving up to 90% by leveraging the cloud ‘spot market’ and avoiding overprovisioning: that’s the promise of Exotanium, a startup enabling users to benefit from Live Virtual Machine Migration – even with stateful workloads – in a transparent way and without interruption

Chip design teams are increasingly resorting to cloud computing, mostly as a way to reduce time-to-market. Running the EDA tools in the cloud, however, can prove extremely expensive, and skyrocketing cloud bills may prevent users from extending the benefits of cloud computing to a larger number of designs. A startup called Exotanium is now offering new solutions to optimize cloud costs, promising savings up to 90%. Cost reduction is obtained by taking advantage, as much as possible, of the cheapest cloud resources (the ones offered through the so-called “spot market”) and by avoiding overprovisioning (that is, paying for cloud resources that are larger in capacity than needed). These achievements were made possible by technologies originally developed at Cornell University (Ithaca, New York). Hakim Weatherspoon, CEO of Exotanium, described the company’s solutions in the video interview he recently gave to EDACafe’s Sanjay Gangal; in this article we will add a few details, as well as the answers provided by Rohan Prakash – Exotanium’s Senior Business Development Manager – to some additional questions.

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With its new ImperasDV solution, the company aims at enabling all RISC-V developers to accomplish the complex task of processor IP verification more efficiently

“The greatest migration in verification responsibility in the history of EDA,” from processor IP vendors to SoC designers: this, according to Imperas Software, is the challenge facing SoC development teams as they take advantage from RISC-V customization capabilities. One of the reasons for the success of RISC-V is undoubtedly the possibility for any SoC developer of adding some degree of customization to the basic instruction set architecture, while saving the processor compatibility with the RISC-V ecosystem of supporting tools and software. The other side of the coin, however, is a heavier verification burden on the SoC development team: as opposed to an off-the-shelf processor IP which is pre-tested by the vendor, a customized processor needs to be verified by whom performed its customization. Addressing this challenge, Imperas Software has recently launched ImperasDV, an integrated solution for RISC-V processor verification.

This new product is the main subject of the video interview that Larry Lapides, Vice-President at Imperas Software, has recently given to EDACafe’s Sanjay Gangal. In this article we will take a closer look at ImperasDV, adding a few details to the video interview content. We will also briefly discuss another major part of Imperas’ product offering, virtual platforms for embedded software development – along with the promotion of open model library availability through the Open Virtual Platforms (OVP) industry consortium. Based near Oxford, UK, with offices in Silicon Valley and Tokyo, Imperas software was founded in 2008 by Simon Davidmann, an EDA veteran.

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Achieving 5x battery life without any hardware changes: according to Deepak Shankar, Mirabilis Design’s founder, this is an example of the benefits that can be obtained through his company’s system-level architecture exploration solution, based on the VisualSim IP libraries

System-level architecture exploration is an increasingly important task for designers, especially when it comes to optimizing power or performance for complex SoC designs. Software company Mirabilis Design (Sunnyvale, CA) has chosen to address this specific area, through a system-level simulation platform – its flagship product VisualSim Architect – that employs IP libraries built in-house. In the last year and a half, the company has seen almost a 6x increase in revenue and almost a 15x jump in the number of customers (source: Mirabilis Design data), partly owing to the new remote collaboration needs brought about by the Covid-19 pandemic. Deepak Shankar, founder and Vice President of Technology at Mirabilis Design, has reiterated the key concepts of his company’s approach in the video interview he has recently given to EDACafe’s Sanjay Gangal. For this article, he has also answered a few additional questions.

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