The European edition of TSMC’s 2024 Technology Symposium – held in Amsterdam on May 14 – allowed EDACafe to gain some additional insights on the innovations that the Taiwan-headquartered foundry first announced on April 24 at the North America edition of the event. Besides providing a roadmap of new opportunities for chipamkers and OEMs, these innovations also shed some light on the strategies that TSMC is planning to pursue over the next few years to retain its world-leading role.
TSMC’s CEO C.C. Wei on stage in Amsterdam. Credit: TSMC
Entering “the Angstrom era” with the A16 process
Among TSMC’s most notable announcements is the upcoming nanosheet-based A16 process, where A clearly stands for Angstrom. Always keeping in mind what IEEE says about process names (i.e. that today they are just marketing labels, with no connection to the real size of transistor features), it’s inevitable to compare TSMC’s A16 process with Intel’s 18A process, and the difference in numbers – 16 vs 18 – suggests that the Taiwanese foundry hopes to leapfrog competitors even in the Angstrom era. According to the figures released by TSMC, the new A16 process – in comparison to the company’s N2P – will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products. The impact of these achievements can be significant considering large datacenters, where a 20% power reduction translates into a big amount of energy in absolute terms. TSMC’s A16 process is best suited for HPC products and is planned to enter production in 2026. As for moving existing designs to the new process, 86% of standard cells can be ported directly from N2P to A16, whereas 16% need a re-optimization.
Credit: TSMC
