Governments around the world keep subsidizing their respective domestic semiconductor industries, with the most recent announcements coming from China and South Korea. Meanwhile, artificial intelligence is accelerating human brain research, with Google spearheading this effort. But first, a few EDA-related updates.

Siemens’ IP quality assurance solution

Siemens Digital Industries Software has introduced Solido IP Validation Suite software, an automated signoff solution for quality assurance across all design intellectual property types, including standard cells, memories and IP blocks. The suite – which includes Siemens’ Solido Crosscheck software and Solido IPdelta software – aims to shorten the time-consuming task of validating IP across all its design views such as logical, physical, electrical, timing, and power analysis contexts. It also provides version-to-version IP qualification for more predictable full-chip IP integration cycles and faster time-to-market.

Siemens’ PyTorch-to-RTL solution for AI accelerator design

Siemens Digital Industries Software has announced Catapult AI NN software for High-Level Synthesis of neural network accelerators on ASICs and SoCs. Catapult AI NN starts with a neural network description from an AI framework such as TensorFlow, PyTorch or Keras, converts it into C++ and synthesizes it into an RTL accelerator in Verilog or VHDL for implementation in silicon. Catapult AI NN brings together hls4ml, an open-source package for machine learning hardware acceleration, and Siemens’ Catapult HLS software for High-Level Synthesis. Developed in close collaboration with Fermilab, a U.S. Department of Energy Laboratory, and other leading contributors to hls4ml, Catapult AI NN enables AI experts to develop PPA-optimized accelerators for different applications without requiring them to become ASIC designers.

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The European edition of TSMC’s 2024 Technology Symposium – held in Amsterdam on May 14 – allowed EDACafe to gain some additional insights on the innovations that the Taiwan-headquartered foundry first announced on April 24 at the North America edition of the event. Besides providing a roadmap of new opportunities for chipamkers and OEMs, these innovations also shed some light on the strategies that TSMC is planning to pursue over the next few years to retain its world-leading role.

TSMC’s CEO C.C. Wei on stage in Amsterdam. Credit: TSMC

Entering “the Angstrom era” with the A16 process

Among TSMC’s most notable announcements is the upcoming nanosheet-based A16 process, where A clearly stands for Angstrom. Always keeping in mind what IEEE says about process names (i.e. that today they are just marketing labels, with no connection to the real size of transistor features), it’s inevitable to compare TSMC’s A16 process with Intel’s 18A process, and the difference in numbers – 16 vs 18 – suggests that the Taiwanese foundry hopes to leapfrog competitors even in the Angstrom era. According to the figures released by TSMC, the new A16 process – in comparison to the company’s N2P – will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15-20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products. The impact of these achievements can be significant considering large datacenters, where a 20% power reduction translates into a big amount of energy in absolute terms. TSMC’s A16 process is best suited for HPC products and is planned to enter production in 2026. As for moving existing designs to the new process, 86% of standard cells can be ported directly from N2P to A16, whereas 16% need a re-optimization.

Credit: TSMC

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An interesting side effect of the so-called “chip war” is that, now, even large news agencies are sometimes delving quite deep into technology topics. News agency Reuters has recently assigned reverse engineering experts to tear down a Huawei phone, to find out who made the chips inside it. The two companies that performed the analysis – iFixit and TechSearch International – found that Huawei’s Pura 70 Pro contains more China-made parts than previous models, highlighting the progress China is making towards technology self-sufficiency. Chinese components found in the high-end phone include a NAND memory that was likely packaged by Huawei’s in-house chip unit HiSilicon, and a Kirin 9010 processor that is likely a slightly improved version of the chip used by Huawei’s Mate 60 series.

Synopsys to sell its Software Integrity Group

After its recent Ansys acquisition, Synopsys is now focusing on EDA by selling its non-EDA division. The company has entered into a definitive agreement with Clearlake Capital Group and Francisco Partners, two global private equity firms, for the sale of its Software Integrity Group business in a transaction with a total value of up to $2.1 billion. Upon completion of the transaction, the business will emerge as a newly independent application security testing software provider. The existing Software Integrity Group management team is expected to lead the new privately held company, whose name has not been announced yet.

Micron to get $6.1 billion CHIPS Act funding

Micron Technology and the Biden-Harris Administration have signed a non-binding Preliminary Memorandum of Terms (PMT) for $6.1 billion in funding under the U.S. CHIPS and Science Act to support planned leading-edge memory manufacturing in Idaho and New York. Construction of the new Boise fab – which will be co-located with Micron’s R&D center – started in October 2023. The Idaho fab is expected to come online and be operational in 2025, with DRAM output starting in 2026. In New York, preliminary design, field studies and permitting applications are underway for the project; construction is expected to begin in 2025, with output starting in 2028.

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