Using AI against EM-IR violations; multi-vendor EDA tools on a single cloud; the 92-billion transistor Apple processor

Risc-V starts attracting attention in the context of U.S.-China “chip war”: a bipartisan group of eighteen U.S. lawmakers that includes five Democrats is reportedly asking the Biden administration to prevent China from achieving dominance in Risc-V technology at the expense of U.S. national and economic security. Let’s now move to this week’s news roundup, starting with some EDA updates.

EDA updates: Cadence, Synopsys, Accellera

The new Cadence Voltus InsightAI is – according to the company – the industry’s first generative AI technology that automatically identifies the root cause of EM-IR drop violations early in the design process and selects and implements the most efficient fixes to improve power, performance, and area (PPA). As Cadence maintains, users of Voltus InsightAI can fix up to 95% of violations prior to signoff, leading to a 2X productivity improvement in EM-IR closure.

The new Synopsys Cloud OpenLink program enables chip designers to seamlessly access EDA tools and IP from multiple vendors in the Synopsys Cloud environment. As part of this initiative, the company is releasing an API specification that Synopsys Cloud OpenLink program members can use to deploy system-level integration with a secure and reliable transfer of entitlements to Synopsys Cloud.

Accellera has announced the availability of the Clock Domain Crossing (CDC) Draft Standard 0.1 for public review. This standard aims to ease SOC integration, which often involves combining in-house and externally purchased IPs. The public review is open through December 31, 2023.

Nvidia’s domain-specific LLM automates language-related chip design tasks

A team of Nvidia researchers has developed ChipNeMo, an artificial intelligence Large Language Model (LLM) specifically adapted to chip design. The work aims to automate time-consuming chip design tasks that involve interfacing with natural languages or programming languages, specifically focusing one three LLM applications: an engineering assistant chatbot for GPU ASIC and architecture design engineers, which understands internal HW designs and is capable of explaining complex design topics; EDA scripts generation for two domain specific tools based on Python and Tcl for VLSI timing analysis tasks specified in English; bug summarization and analysis as part of an internal bug and issue tracking system. To cost-effectively train domain-specific models, Nvidia combined the following techniques: Domain-Adaptive PreTraining (DAPT) of foundation models with domain adapted tokenizers, model alignment using general and domain specific instructions, and retrieval-augmented generation (RAG) with a trained domain-adapted retrieval model. Results show that these domain adaptation techniques enable significant LLM performance improvements over general-purpose base models, enabling up to 5x model size reduction with similar or better performance. The research paper can be found here.

New Apple processors

Apple has announced the new generation of its internally designed, Arm-based Mac processors: M3, M3 Pro, and M3 Max, built using the 3-nanometer process technology. The M3 family of chips features a new GPU that introduces a new technology called Dynamic Caching. Unlike traditional GPUs, Dynamic Caching allocates the use of local memory in hardware in real time, so that only the exact amount of memory needed is used for each task, increasing the average utilization of the GPU. According to Apple, rendering speeds are now up to 2.5x faster than on the M1 family of chips. The CPU ‘performance cores’ and ‘efficiency cores’ of the M3 family are 30 percent and 50 percent faster than those in M1, respectively, and the Neural Engine is 60 percent faster. A new media engine now includes support for AV1 decode. The M3 family features a unified memory architecture supporting up to 128GB. The most powerful member of the family, M3 Max, pushes the transistor count up to 92 billion. It features a 40-core GPU and a 16-core CPU.

Extending Risc-V ISA with security instructions

Codasip has announced the first commercial implementation of CHERI (Capability Hardware Enhanced RISC Instructions), a security mechanism developed at the University of Cambridge. As explained in a press release, CHERI extends conventional hardware Instruction Set Architectures to enable fine-grained memory protection and highly scalable software compartmentalization. This allows historically memory-unsafe programming languages such as C and C++ to be adapted to provide protection against many widely exploited vulnerabilities. Using Codasip Studio, Codasip is adding built-in fine-grained memory protection to its recently launched 700 processor family by extending the Risc-V ISA with CHERI-based custom instructions. To enable the use of these instructions, Codasip is also delivering the software environment to take advantage of CHERI technology.

Accelerating ReRAM time to market

SureCore and Intrinsic collaborate to accelerate time to market for Intrinsic’s Resistive Random-access Memory (ReRAM) technology. According to the two companies, Intrinsic’s ReRAM will address the challenges faced by SoC developers seeking an embedded non-volatile storage solution for 22nm and smaller nodes, now that flash is no longer a viable option. Intrinsic claims that ReRAM has many compelling advantages including flash-like density coupled with SRAM access times. Additionally, ReRAM can easily be built on the same advanced process nodes as the logic, reducing power consumption and removing potential data bandwidth bottlenecks and latency caused by using off-chip flash memory.

UMC’s wafer-to-wafer 3D IC partnership

Taiwanese foundry UMC has initiated its W2W (wafer-to-wafer) 3D IC project – in collaboration with partners Winbond, Faraday, ASE, and Cadence – to help customers accelerate the development of their 3D products. The project offers an end-to-end solution for integrating memory and processor with silicon stacking technology.

Deals

Jabil will take over the manufacture and sale of Intel’s current Silicon Photonics-based pluggable optical transceiver product lines and the development of future generations of such modules.

SiTime has entered into an exclusive agreement with Aura Semiconductor to acquire its clock products and license all its clock IP.

Further reading

German think tank “Stiftung Neue Verantwortung” has published an analysis of technology partnerships among governments around the world. The 64-page paper was prepared by examining more than 150 public government documents. Below is a table visually representing some of the partnerships analyzed in the report.

Credit: Stiftung Neue Verantwortung

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