EDACafe Editorial Roberto Frazzoli
Roberto Frazzoli is a contributing editor to EDACafe. His interests as a technology journalist focus on the semiconductor ecosystem in all its aspects. Roberto started covering electronics in 1987. His weekly contribution to EDACafe started in early 2019. Intel’s new operating model; investments in India; Stellantis-Foxconn JV; a 51.2 Tbps SerDesJune 26th, 2023 by Roberto Frazzoli
A fund backed by the Japanese government has reportedly agreed to buy Japanese photoresists supplier JSR. The deal would represent an additional effort of the Japanese government to revitalize its domestic semiconductor industry. Among the other interesting news this week, Intel implicitly admitting (in this press release) that it is currently spending up to $1.5 billion per year due to operational inefficiencies that its competitors don’t have. This refers to expedited wafers and test times, as explained below. Intel to adopt an internal “fabless-foundry” model Intel will adopt a new operating model where its internal product groups will move to a foundry-style relationship with the company’s manufacturing group. In this new “internal foundry” model, Intel’s product business units will engage with the company’s manufacturing group in a similar fashion that fabless semiconductor companies engage with external foundries. Intel’s manufacturing groups will be accountable to a standalone profit and loss (P&L) for the first time. The company expects this change to boost efficiency and therefore deliver significant cost savings. One example concerns “expedited” wafers that business units decide to move through Intel’s manufacturing process, which are costly and reduce factory efficiency. Going forward, this service charge will be borne by the business units, and it’s expected that it will reduce the number of expedites “to be on par with the competition”. Another example concerns Intel’s test times, which currently run “double or triple those of competitors”. As business units are charged market prices based on test time, Intel expects pre-silicon design choices to reduce these test times.
U.S. tech investments in India: Micron, Applied Micron has announced plans to build a new assembly and test facility for both DRAM and NAND products in Gujarat, India. The new facility will address demand from domestic and international markets. Phased construction of the new assembly and test facility in Gujarat is expected to begin in 2023. Phase 1, which will include 500,000 square feet of planned cleanroom space, will start to become operational in late 2024. The Indian government has reportedly agreed production-linked incentives worth $1.34 billion for the plant. Applied Materials intends to build an engineering center in Bangalore, India, focused on development and commercialization of technologies for semiconductor manufacturing equipment. The center will bring together Applied engineers, global and domestic suppliers, and research and academic institutions. Applied intends to make a gross investment of $400 million over four years to establish the new center in India. Stellantis-Foxconn joint venture to design and sell automotive chips Automaker Stellantis and Taiwanese EMS Foxconn have announced the creation of SiliconAuto, a 50/50 joint venture dedicated to designing and selling a family of state-of-the-art semiconductors to supply the automotive industry, including Stellantis, starting in 2026. SiliconAuto will be headquartered in the Netherlands. Stellantis is the automaker group behind several European and U.S. car brands including Alfa Romeo, Chrysler, Citroën, Dodge, Fiat, Jeep, Maserati, Opel, Peugeot, Vauxhall, and more. Integrating air-filled waveguides into low-cost PCBs Belgian research center imec and Austria-headquartered PCB manufacturer AT&S have demonstrated an approach for integrating air-filled substrate-integrated waveguide (AFSIW) technology into a multilayer PCB. The resulting solution, according to imec, is the world’s first implementation of D-Band AFSIWs in a low-cost, mass-manufacturable PCB – coming with a five-fold loss reduction. This new approach paves the way for the development of compact, cost-effective, and high-performance 140 GHz (automotive) radar and 6G mobile communications systems, offering significantly lower signal loss in comparison to planar PCB lines or substrate-integrated waveguides (SIWs) in PCBs and interposers. Cisco’s 51.2 Tbps SerDes Cisco has announced its fourth generation set of devices targeting Ethernet-based AI/ML networks, the Silicon One G200 and Silicon One G202. The Silicon One G200 is a 5-nanometer, 51.2 Tbps, 512 x 112 Gbps SerDes device. The Silicon One G202 is a 5-nanometer, 25.6 Tbps, 512 x 56 Gbps SerDes device with the same characteristics as the Silicon One G200 but with half the performance. The Silicon One devices employ an analog-to-digital (ADC)-based SerDes technology. According to Cisco, the new devices enable users to build a 32K 400G GPUs AI/ML cluster with a 2-layer network requiring 50% less optics, 40% fewer switches, and 33% fewer networking layers. Will lasers and satellites replace deep-sea cables? A team led by Swiss university ETH Zurich has demonstrated terabit optical data transmission using a laser, over a 53 kilometers (33 miles) distance. According to ETH Zurich, in the future this technology will make it possible to create Internet backbone connections via near-Earth satellite constellations that are significantly less costly than deep-sea cables. Internet connections via satellite are not anything new, but usually such technologies operate in the microwave range. Laser optical systems, in contrast, operate in the near-infrared range and can transport more information per unit of time. The terabit performance has been achieved using a new four-dimensional BPSK (4D-BPSK) modulation format which encodes the information bits in properties of the light wave such as amplitude, phase and polarization, enabling detection with as little as 4.3 photons per bit. The laser’s light waves are sent and received through telescopes. The turbulence of the air particles results in varying speeds of light waves and can produce errors; to prevent them, a MEMS chip with a matrix of 97 tiny adjustable mirrors correct the phase shift of the beam. Deals Intel will sell an approximately 20% stake in its Austria-based IMS Nanofabrication business to Bain Capital, in a transaction that values IMS at approximately $4.3 billion. The transaction is expected to close in the third quarter of 2023. IMS will operate as a standalone subsidiary and will continue to be led by CEO Dr. Elmar Platzgummer. IMS is the inventor of the multi e-beam technology for mask writing. Intel initially invested in IMS in 2009 and ultimately acquired the business in 2015. Further reading A Reuters report investigates China’s underground market for A100 Nvidia AI chips, which are subject to export restrictions. |