CHIPS Act updates; single-SoC automotive architecture; neural rendering; 2022 IEEE roadmap

New developments have emerged on the implementation of the U.S ‘CHIPS and Science Act’. More news this week include both Nvidia and Qualcomm advocating the unification of automotive electronic functions in a single system-on-chip. But first, an EDA update.

Synopsys’ unified emulation and prototyping system

Synopsys has announced what it claims is “the industry’s first” unified hardware system for emulation and prototyping, based on its ZeBu EP1 emulation system. Unification enables a single verification hardware system to be used throughout the entire chip development lifecycle. According to Synopsys, users of the ZeBu EP1 system have achieved 19 MHz emulation and 100 MHz prototyping clock performance, enabling them to run large amounts of software pre-silicon and accelerate project schedules. The unified hardware system allows users’ verification and software development requirements to drive how and when to shift capacity between emulation and prototyping, rather than having to estimate early on how much of each resource might be needed.

U.S. CHIPS Act updates: leadership team, innovation coalition

The U.S. government has announced the leadership team which will be responsible for the implementation of the CHIPS and Science Act. Members of the team are Ronnie Chatterji, Michael Schmidt, Eric Lin, Todd Fisher, Donna Dubinsky, and J.D. Grom. Individual roles and bios are detailed in this press release.

More than 100 businesses, startups, universities and nonprofits have formed the American Semiconductor Innovation Coalition (ASIC) with the specific goal of being selected by the Department of Commerce as the partner of choice for the newly created ‘National Semiconductor Technology Center’ and ‘National Advanced Packaging Manufacturing Program’ – both funded through the recently passed ‘CHIPS and Science Act’. Among others, ASIC members include AMD, Analog Devices, Ansys, Applied Materials, Cadence, DuPont, GlobalFoundries, IBM, KLA, Microsoft, Micron, MIT, Nvidia, Samsung, Siemens EDA, Synopsys, Texas Instruments. Some of the coalition members are headquartered in Europe, such as ASML, CEA-Leti, Fraunhofer, imec and Yole Développement. In terms of academic institutions, the ASIC member list currently published on the coalition website does not include neither Stanford University nor UC Berkeley. ASIC claims the ability to stand up an NSTC innovation hub in as little as six months. Among its key capabilities, the coalition mentions the already existing Albany NanoTech Complex.

Unified automotive SoCs: Nvidia’s Drive Thor VS Qualcomm’s Snapdragon Ride Flex

Recent announcements from both Nvidia and Qualcomm indicate a clear trend towards automotive architectures based on the unification of all the vehicle functions in a single super-powerful system-on-chip. On occasion of its recent GTC event, Nvidia introduced Drive Thor, its new automotive SoC. The chip, which achieves up to 2,000 teraflops of performance, unifies intelligent functions — including automated and assisted driving, parking, driver and occupant monitoring, digital instrument cluster, in-vehicle infotainment and rear-seat entertainment — into a single architecture. Drive Thor supports multi-domain computing, isolating functions for automated driving and in-vehicle infotainment. On one computer, the vehicle can simultaneously run Linux, QNX and Android. According to Nvidia, consolidating many functions on a single SoC eases supply constraints and simplifies vehicle-design development, resulting in significantly lower cost, less weight and fewer cables. In terms of AI capabilities, essential for self-driving, the innovations introduced by Drive Thor include an inference transformer engine and the ability to use an 8-bit floating point (FP8) data format. Designed to be ASIL D functionally safe, the chip will be available for automakers’ 2025 models.

At its recent Automotive Investor Day, Qualcomm introduced what it described as “the industry’s first integrated automotive super-compute class System-on-Chip,” the Snapdragon Ride Flex SoC. The chip combines cockpit, driver assistance, automated driving and networking functions, in a unified architecture for “mixed criticality” workloads. The announcement was made on stage by Qualcomm’s Nakul Duggal, who only disclosed a few details about the new SoC including the performance – 2000 TOPS – of the most powerful member of the family.

A snapshot from the video recording of Qualcomm Automotive Investor Day, showing Nakul Duggal introducing the Snapdragon Ride Flex SoC. Credit: Qualcomm

Nvidia’s new GPUs using ‘neural rendering’

At the GTC event, Nvidia also unveiled the GeForce RTX 40 Series of GPUs for gamers and creators. The flagship product in this series, the RTX 4090 GPU, claims up to 4x the performance of its predecessor. According to Nvidia, the RTX 40 Series represents a new era of real-time ray tracing and ‘neural rendering’, the technique which uses AI to generate pixels. An overview of the state of the art of neural rendering can be found here.

New interchangeable format for AI data

Arm, Intel and Nvidia have jointly authored a paper describing an 8-bit floating point (FP8) specification and its two variants E5M2 and E4M3 to provide a common interchangeable format that works for both artificial intelligence training and inference. As explained in a press release, this cross-industry specification alignment will allow AI models to operate and perform consistently across hardware platforms, accelerating AI software development.

2022 edition of the International Roadmap for Devices and Systems

IEEE has published the 2022 edition of the International Roadmap for Devices and Systems (IRDS). An executive summary of the new edition can be found here. Among the topics covered by the IEEE experts, an interesting consideration on the future 6G networks: “The frequency spectrum allocated to 6G ranges from 95 GHz to 1 THz. It is clear from the [Friis] formula that the practical wireless radius of 6G will be limited to only a few feet! This implies that the distribution network needs to be completely reengineered. This completely new network needs to be constructed to propagate information propagating at these frequencies via a physical network. In essence, the performance required can only be guaranteed by using fiber optics,” IEEE concludes.

X-FAB foundry adds a SiGe BiCMOS process

Germany-headquartered foundry X-FAB has added a silicon-germanium BiCMOS 130-nanometer process promising higher performance for advanced communication systems – such as Wi-Fi 6 (and future Wi-Fi 7) access points, 5G and 6G cellular infrastructure, vehicle-to-vehicle communication, and +100 GHz radar systems. The addition is the result of a license agreement with the Leibniz Institute for High Performance Microelectronics (Germany), which developed this SiGe BiCMOS technology.

Keysight’s 256 GSa/s arbitrary waveform generator

Keysight has introduced the new M8199B arbitrary waveform generator, a signal source for arbitrary signals with sampling rate up to 256 GSa/s and analog bandwidth exceeding 80 GHz, including up to eight synchronized channels operating simultaneously. Main application area of the new instrument is R&D for designs employing multi-level modulation formats (e.g. 64QAM) at well beyond 160 GBaud.

Acquisitions

FPGA vendor Achronix has acquired the Ethernet FPGA IP catalog of Accolade Technology, as well as Accolade’s technology team. The acquired IP provides a full-function Ethernet shell for Achronix Speedster FPGA, VectorPath accelerator card and Speedcore eFPGA products.

Altair has completed the acquisition of RapidMiner, a specialist in advanced data analytics and machine learning software.

Upcoming events

SPIE Photomask Technology/Extreme Ultraviolet Lithography will run from September 25 to 29 in Monterey, CA.

GSA U.S. Executive Forum will be held on September 27 in Menlo Park, CA.

IEEE/ACM International Symposium on Microarchitecture is scheduled for October 1-5 in Chicago, IL.

iMAPS (International Symposium on Microelectronics) will take place from October 3 to 6 in Boston, MA.

Vision – a trade fair on machine vision – is scheduled for October 4 to 6 in Stuttgart, Germany.

Electronic Design Process Symposium will take place on October 6 and 7 in Milpitas, CA. Among the presentations, Chronos Tech will address “The Dawn of Clockless Technology”, and University of Maryland will discuss how Dynamic Voltage Scaling can be exploited to break the trusted execution environment (TEE) provided by Arm TrustZone, Intel SGX, and Nvidia GPU Cloud.

This entry was posted on Friday, September 23rd, 2022 at 1:22 pm. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.