The so-called metaverse now has its standardization initiative: called Metaverse Standards Forum, it brings together a few dozen founding members including Meta (Facebook), Microsoft and Nvidia – but, as noted by Reuters, the member list currently does not include Apple. However, “the Forum is open to any company, standards organization, or university at no charge,” says the announcement press release, so never say never. Let’s now move to our usual news round-up, that this week includes a couple of interesting academic works.
Quick EDA updates
Keysight’s PathWave RFPro, integrated with the Synopsys Custom Compiler design environment, is enabled to support TSMC’s newest N6RF Design Reference Flow.
Pulsichas added new features to its Unity product. Among them, Unity Chip Planning technology now can handle incremental floorplans; and the embedded integrations with Cadence Virtuoso and Synopsys Custom Compiler allow users to access Unity directly from these systems.
Cadence’s Design IP offering has already achieved over twenty design wins in TSMC’s 5nm process technology, with multiple first-pass silicon successes.
Xpeedichas recently released its latest RF EDA/Filter Design Platform 2022.
Geopolitical issues keep making news: a team of U.S. investors, scientists, operators, and national security experts has founded America’s Frontier Fund (AFF), described as “the nation’s first non-profit strategic investment fund focused on building and scaling breakthrough deep-tech companies and platforms for the national interest.”. Led by CEO and co-founder Gilman Louie, AFF intends to counter “authoritarian nations” that “are committed to out-spending and out-innovating the U.S. to gain military and economic superiority.” The fund’s initial areas of focus will include microelectronics, artificial intelligence, new materials, quantum sciences, next generation networks (5G/6G), advanced manufacturing, and synthetic biology. Let’s now move to other news updates, this week with a significant presence of European research centers.
Imec demonstrates backside power delivery with buried power rails
Belgian research institute Imec has demonstrated a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). The BPRs connect to scaled FinFET devices whose performance was not impacted by backside wafer processing. The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm and beyond), as the nTSVs land on BPRs with tight overlay control and are implemented at a tight pitch of 200nm without consuming any area of the standard cell. The solution also offers a system performance benefit by improving the power delivery, as it reduced IR voltage drop. Additionally, Imec demonstrated a performance boost by implementing a 2.5D MIMCAP (metal-insulator-metal capacitor) in the backside serving as a decoupling capacitor. Backside power delivery – using the back side of the wafer to route power lines, in order to alleviate routing congestion on the front side and reduce IR voltage drop – can be implemented in different ways; Imec believes that combining it with buried power rails is the most promising implementation scheme.
TEM image showing scaled FinFET devices connected to the wafer’s backside (through nTSVs and BPR) and frontside (through BPR, VBPR and MOA). Copyright: Imec
According to Reuters reports on the impact of Ukraine war, more U.S. tech companies are leaving Russia: Microsoft is substantially cutting its activity in the country, while IBM is closing its Russian business and has started to lay off its employees. Russia, for its part, has limited exports of noble gases including neon – used in chip fabrication – until the end of 2022. Exports will be allowed only with special State permission. Let’s now move to our usual tech news round-up, starting with a brief update on TSMC’s roadmap: the Taiwanese foundry has reportedly chosen the nanosheet transistor architecture for its next 2-nanometer node starting in 2025. As for EDA, the use of artificial intelligence/machine learning in chip design is in the spotlight this week with two significant announcements.
Synopsys has introducedDesignDash, a design optimization solution based on machine learning and big data analytics. According to the company, DesignDash enhances design productivity in different ways: by providing real-time design status through visualizations and interactive dashboards; deploying deep analytics and machine learning to extract and reveal actionable understanding from vast volumes of structured and unstructured EDA metrics and tool-flow data; classifying design trends, identifying design limitations, providing guided root-cause analysis and delivering flow consumable, prescriptive resolutions. The solution complements the Synopsys SiliconDash product, part of the Synopsys Silicon Lifecycle Management Family.
China is among the themes of this week’s roundup, with news concerning both its richly funded AI chip providers and – despite growing geopolitical tensions – its attractiveness for European investments.
Merck to build a new site in China
Germany-based Merck KGaA has reportedly signed a contract to open a base in the Chinese city of Zhangjiagang, describing it as its largest single electronics business investment in the country. In the new site, a 69-acre lot, Merck will build production facilities for thin film materials and electronic specialty gasses, along with a warehouse and operation centers. “China is currently the fastest growing semiconductor manufacturing market worldwide,” Merck China President Allan Gabor reportedly said in a statement. “We believe a golden era for China’s semiconductor industry has just begun,” he added.
Will Ukraine war accelerate transition to electric vehicles?
War in Ukraine is causing a shortage of wire harnesses – the complex and heavy cable bundles connecting all the electrical/electronics components of a vehicle – as the Eastern European country is a major supplier of these products. The shortage could accelerate transition from traditional vehicle network architectures based on “domain ECUs” to the new architectures based on “zonal ECUs”, which enable a dramatic simplification of vehicle wiring. This, at least, is the opinion of the industry experts quoted in a recent Reuters report. Simpler and lighter cable bundles would reduce carmakers dependence on Ukraine and other countries with a low labor cost, but their adoption would require redesigning the vehicles’ data and power networks. This could prompt a quicker phase-out of gasoline and diesel vehicles, as carmakers would rather not invest money in redesigning products that are approaching the end of their lives. Zonal ECUs are also paving the way to new wiring technologies such as the flexible circuits developed by CelLink (San Carlos, CA), already being used in ‘native’ electric cars.
