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Archive for July, 2022

SaaS-based system design and analysis goes e-commerce with Cadence OnCloud

Friday, July 29th, 2022

OrCAD and Allegro PCB design technologies, Clarity/Sigrity/Celsius system analysis technologies, and Fidelity CFD software are now available from a SaaS platform, through a consumption-based pricing model

Ease of purchase is undoubtedly one of the reasons for success of many consumer-oriented services provided through the Internet: just type a card number, freely select a quantity or a subscription duration, and you immediately get what you want. With EDA technologies now available through cloud computing platforms, this ease of purchase can also be extended to the use of EDA tools – adding to the main benefit of a Software-as-a-Service model: eliminating the need for expensive infrastructure hardware. These, in short, are the concepts behind OnCloud, the new Cadence e-commerce platform for cloud-based system design and analysis. With OnCloud, the ease of purchase enabled by e-commerce is leveraged to address two types of customer needs: on the one hand, making it easier for the ‘long tail’ of small EDA users to access first-class technologies; on the other hand, enabling big EDA users to cope with workload peaks without purchasing additional licenses. Two Cadence executives – Ben Gu, Vice President of R&D for the Multiphysics System Analysis Business Unit, and Mahesh Turaga, Vice President of Business Development, Cloud – described the OnCloud features in the video interview they recently gave to EDACafe’s Sanjay Gangal; in this article we will add a few details, as well as the answers Turaga provided to some additional questions.


Turnkey ASIC outsourcing – Presto Engineering’s proposal to Original Device Manufacturers

Friday, July 22nd, 2022

According to the European company specializing in semiconductor design and services, it is now possible to bring an ASIC to market for less than $5 million dollars in upfront investment – and customers lacking semiconductor expertise can lower the risks by outsourcing to Presto the entire ASIC procurement process, from design to delivery

It’s a two-speed world: on the one hand, applications such as smartphones or artificial intelligence accelerators keep pushing the semiconductor industry towards Angstrom-scale process nodes and hundreds of billions transistor counts; on the other hand, many end products in a variety of markets – from industrial to medical and more – are still relying on an electronic box containing a PCB with a number of low-integration ICs and discrete components. Replacing the old-style box with an ASIC would clearly provide multiple benefits to the end product, but manufacturers lacking a semiconductor expertise are concerned by the risks of a complex production process. Targeting this largely untapped market, a France-headquartered company called Presto Engineering is addressing European and American manufacturers with a two-pronged message: ASICs are now cheaper and easier to make than ever before, and risks can be reduced by outsourcing the entire ASIC procurement process – from design to delivery – to Presto. Michel Villemain, CEO of Presto Engineering, described his company’s offering in the video interview he recently gave to EDACafe’s Sanjay Gangal; in this article we will add a few details, as well as the answers he provided to some additional questions.


AI-driven system design optimization with Cadence Optimality Explorer

Friday, July 15th, 2022

From a chip to another, traveling through a package, a printed circuit board, and another package: the trip of a high-speed electric signal inside a system is fraught with perils. And avoiding that signals arrive weak and ‘dirty’ at their final destinations is just one of the system-level challenges facing designers today: with ever higher package densities, finer PCB traces, and higher frequencies, crucial aspects now include cooling, stress and more. At the system level, therefore, the interactions among electrical, mechanical, electromagnetic and thermal aspects can no longer be neglected. Unfortunately, the combination of so many different parameters generates an immensely large design space, that system designers are supposed to thoroughly explore to find the optimal solution.

Besides being very human-intensive and requiring a lot of time and computing resources, this task is often hindered by organizational ‘silos’ preventing collaboration among experts from different disciplines. Now a new solution from Cadence, called Optimality Explorer, promises a ten times faster system design optimization – with up to a 100X speedup on some designs – by applying artificial intelligence to a “Multi-disciplinary analysis and optimization” (MDAO) approach. Ben Gu, vice president of R&D for the Multiphysics System Analysis Business Unit at Cadence, described Optimality in the video interview he recently gave to EDACafe’s Sanjay Gangal; in this article we will add a few details, as well as the answers he provided to some additional questions.

A quick look at the DAC 2022 conference program

Friday, July 8th, 2022

The Design Automation Conference is back to its usual summer timeframe – again at the Moscone Center in San Francisco – with over one hundred exhibitors and a rich conference program that covers a wide range of topics including artificial intelligence, autonomous systems, Risc-V, security, embedded systems and more. Here we will briefly highlight some of the conference content more directly related to EDA, referring readers to the conference program for the detailed schedule.

EDA vendors’ top executives on stage: keynotes and panels

As usual, the DAC will offer attendees the opportunity to listen to EDA vendors’ top executives and – to some extent – to ask them questions. This year’s keynoters will include Anirudh Devgan, Cadence CEO, speaking about “Computational Software and the Future of Intelligent Electronic System Design”. More EDA executives will give speeches as part of a series called SKYTalks: Joe Sawicki from Siemens EDA (“Delivering ‘Smarter’ Faster: The Future of EDA & AI”), and Sandeep Mehndiratta from Synopsys (“It’s Getting Cloudy Out There”). Among the panels featuring EDA vendor executives, the top spot obviously goes to John Cooley’s DAC Troublemaker Panel, offering attendees the opportunity to hear “edgy questions” being asked to Joe Sawicki (Siemens EDA), Tom Beckley (Cadence), Dean Drako (IC Manage), Prakash Narain (Real Intent), Tony Chan Carusone (Alphawave IP) and Sam Appleton (Ausdia).


Samsung’s 3-nm GAA in production; training large NLP models on a single Cerebras device; reducing metal line resistance

Friday, July 1st, 2022

Quick updates on the impact of Ukraine war. Global exports of semiconductors to Russia have reportedly slumped by 90% due to export controls. And U.S. Commerce Secretary Gina Raimondo has reportedly threatened to “shut down” China’s SMIC foundry if it is found to be supplying chips to Russia. “We will shut them down and we can, because almost every chip in the world and in China is made using U.S. equipment and software,” she said. Moving to new fab updates, Taiwan’s GlobalWafers will reportedly invest $5 billion on a new plant in Sherman, Texas, to make 300-millimeter silicon wafers, switching to the United States after a failed investment on Germany’s Siltronic.

Samsung’s 3-nm GAA in production

Samsung Electronics has announced that it has started initial production of its 3-nanometer process node applying its Gate-All-Around (GAA) transistor architecture called Multi-Bridge-Channel FET (MBCFET), enabling a supply voltage reduction and a higher drive current capability. Initial applications are targeting high performance, low power computing, with plans to expand to mobile processors. According to the company, Samsung’s proprietary technology – which utilizes nanosheets with wider channels – allows higher performance and greater energy efficiency compared to GAA technologies using nanowires with narrower channels. However, channel width in Samsung’s 3nm GAA technology can be adjusted to obtain various power/performance combinations. Compared to 5nm process, Samsung claims that the first-generation 3nm process can reduce power consumption by up to 45%, improve performance by 23% and reduce area by 16%; the second-generation 3nm process is expected to reduce power consumption by up to 50%, improve performance by 30% and reduce area by 35%.

Photo: Business Wire


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