Discovering Cadence Integrity 3D-IC platform

Cadence’s Vinay Patwardhan explains how designers can tackle the challenges posed by 3D ICs using the new solution recently announced by the company

Placing multiple chips in a single package – either in a 2.5D or in a 3D fashion – is emerging as a viable solution to continue advancing IC performance and functionalities using the currently available process nodes, while keeping die size within lithography reticle limits. However, a package containing two or more dies can be considered as a new type of system, posing new system-level challenges. Existing EDA tools – even the most advanced ones – are mostly meant to address the challenges posed by a single chip and its package; for this reason, the EDA industry is now coming up with new solutions specifically addressing the needs of 2.5D and 3D ICs. Cadence, in particular, has recently announced a new platform called “Integrity 3D-IC”, which it describes as the “industry’s first comprehensive 3D-IC platform for multi-chiplet design and advanced packaging”. To know more about this solution, EDACAfe’s Sanjay Gangal has conducted a video interview with Vinay Patwardhan, Product Management and Group Director, Digital and Signoff Group at Cadence Design Systems.

Process shrink slowdown and reticle size limits are driving the trends towards 3D ICs

Patwardhan started out by recalling the reasons behind the 3D IC trend. “Recently, we’re hearing a lot of activity in 3D IC,” he said. “The concept of 3D has been around [for some time], but a couple of things are happening. One is that the industry is designing chips at five nanometer, three nanometer, and we don’t know what’s after that. Actually the physical limitation of the transistor is being reached beyond three; there may be a two [nanometer node] and who knows what’s after that. So in order to continue the scaling of Moore’s law, everyone is looking for new techniques, what is the best way to continue doubling the number of transistors or improving the functionality that can be offered by a single design on a single package. Another thing – he continued – is that if you see some of the large GPU makers, large CPU makers, their die size is extremely big. We know that there is a physical limitation on the reticle size of the lithography machines of about 853-square millimeters, and some of these die sizes for large GPUs, large CPUs are almost in the range of 800-square millimeters now, 750 to 800. And the yield is also very low. How to get around that and continue innovation? One easy way is to go 3D and start stacking chips on top of each other, or start placing chips next to each other connected by an interposer layer.” As Patwardhan explains, with hyperscalers’ datacenters and other advanced applications driving the need for high-performance processors, “suddenly 3D has now become the way to go. It would be a solution to address the slowdown of the Moore’s law as well as the reticle size limit. And it’s normally an easy solution – on paper, at least – to stack chips and then get around all these challenges that are being posed.”

New mechanical and thermal challenges and the need for SOC-package co-design

Stacking chips is a smart way to work around scaling and reticle limitations, but the practical implementation of this concept involves many new challenges. “It’s easier said than done,” Patwardhan pointed out. “It’s easy to just say, stack things like two Lego blocks, but when you are stacking chips, you are actually putting physical weight on the chip at the bottom, so there are effects like mechanical stress. And if switching on both chips is happening at the same time, there is thermal effects that you have to look at. So when you’re stacking chips, it becomes like a whole system. And [even the package] has to be modified, because there are multiple dies that are being stacked on each other. One of the big challenges that happen when you are making 3D ICs is that package design has to be redone. Normally package and SOC teams work in silos up to a certain point, then they start exchanging data and they realize ‘I need to modify something in the package, I need to redesign something on the SOC.’ 3D-ICs [further increase] the level of difficulty (…), so there has to be some kind of co-design between the package and the chips that are being stacked.”

More challenges: bumps and vias location, system-level checks

More 3D IC challenges stem from the need to build a properly working 3D structure, connecting all the right signal lines in the right way, even when assembling multiple chips that can be very different from one another. And once such a structure is created, it should be considered as a system and analyzed in a holistic way. “These stacked chips may be in different technology nodes,” Patwardhan pointed out. “Today also it’s possible to do that, but it’s a very die-by-die method. So you do one chip at a time and then you exchange abstracts, see whether the bumps are fitting on top of each other, that the through-silicon vias are placed correctly and there’s enough clearance around those. [It] is a very iterative and long process. If something can be combined in one system, in one view or a single cockpit, then that will really help address that challenge. And then, of course, as I mentioned, there are system-level effects, which are additional verification that a 3D IC system will have to do than just closing timing, power and EMI and the stuff that you do in a regular SOC design. Some of these additional system-level checks have to be understood, taken into account, and then applied before building a robust 3D IC system.”

Requirements for a 3D EDA solution: unified cockpit, unified database, advanced packaging tools

Overcoming the new challenges posed by 3D IC design calls for new EDA tools featuring new functionalities. “First of all, you need some kind of a unified environment where all these pieces can be put together,” Patwardhan said. He also underlined the need for more advanced packaging design tools: “Package is just a passive element, and an interposer or some connective layer is also passive, but it’s a silicon layer (…) From an EDA point of view, our tools that we have for package designs will not work for some of these silicon interposer type of design. So we need more IC-like tools, something that is more numerical, computational, that takes into account the placement, simultaneous optimization, multi-objective placement. Some of these algorithms that we use in our standard place-and-route tools have to be expanded to the third dimension to take into account the Z direction. Another thing is that all these pieces are in different technology nodes, so we need a representation in a single database to handle them, identify them hierarchically as separate pieces and then give the system-level designer a way to not just build the design, but do early analysis to make sure that the design is robust and he’s able to take it to closure in an acceptable timeline.”

Cadence’s answer: Integrity 3D-IC, a new platform bringing “leading technologies” together

According to Patwardhan, the answer to all these challenges is Cadence’s new Integrity 3D-IC platform, which builds upon a foundation of several preexisting Cadence tools. “We at Cadence have had tools for package designs for the last fifteen or twenty years now, and we have had tools for SOC design for the last few years,” he said. “They are all market leading technologies like Virtuoso and Allegro. Integrity 3D-IC is a new platform that brings all of these leading technologies together. It is a unified platform for doing 3D design planning and 3D implementation. It can do early analysis of timing, power, EM/IR, inter-die LVS/DRC and thermal analysis, which is one of the most important analysis. So, all that in one unified platform, where we can get early feedback from the system level analysis and enable what we are calling ‘system-driven PPA’: taking feedback from the system and improving the power, performance and area of the chips that are going into a 3D IC system.”

Addressing a variety of 2.5D and 3D styles

Getting deeper into the details of the functionalities offered by Integrity 3D-IC, Patwardhan first of all pointed out the platform’s capability to handle different 2.5D and 3D styles. “3D IC means a lot of different things to different people,” he said. “When we were thinking of building a comprehensive platform, we’ve really wanted to make sure it does encompass everything that’s offered in the industry.” Patwardhan then briefly mentioned some of the 3D packaging styles offered by leading foundries, such as the InFO (Integrated Fan-Out) wafer level packaging from TSMC, the 2.5D designs where a silicon interposer or an RDL interposer connects a processor and an HBM, the full-stack designs with an image sensor array on the top layer. “Integrity 3D-IC does cover all of these types of designs,” he said. “We do have the technology, either through (…) Innovus or any of the Cadence individual technologies. We have all of them, so whatever 3D IC means to whoever is doing it, Integrity 3D-IC should have an offering for that. It is a comprehensive, single compact tool for all types of 3D IC designs.”

Partitioning capabilities for top-down 3D IC design

Other key features offered by Integrity 3D-IC are meant to enable a top-down design approach. “Today, the 3D IC designs that we are seeing in the industry are mostly bottom up,” Patwardhan noted. “That means dies are designed individually, and then it’s decided that this particular die with some minor modifications should go into a 3D IC system. And then IPs are bought off the shelf and put around on those. That’s the methodology today – but is that optimal going forward? is that the only method to go forward? There’s still a lot of research and industry debate going on. We have this 3D partitioning capability in Integrity 3D-IC, for actual top-down design,” Patwardhan pointed out. “Let’s say you have a high-performance processor that today is working at certain X frequency; by splitting that into two dies and by separating out the memory components on the top die and all the standard cell logic on the bottom die, is there a way to improve the frequency or reduce the power? Any kind of exploration like that is possible with Integrity 3D-IC. So, we do have this top-down flow. Currently we have enabled it for memory on logic, and the reason is that memories sometimes scale differently than logic at advanced nodes. A lot of our customers want to explore that flow: if I separate out all the registers memory in a separate die and have all the logic switching at the bottom die, will that be a good 3D IC configuration? And because the wire length is low – less than standard 2D – there’s definitely going to be an improvement in power. Areas, of course, is smaller because it’s two small chips (…), and since the timing paths are shorter, you’re able to push the frequency beyond a certain limit using this flow. Then you mount [the dies] on a package, and you can perform all the system-level analysis. So this top-down flow is also what’s new and available through Integrity 3D-IC platform.”

3D IC system-level analysis

According to Cadence, Integrity 3D-IC can also address the new analysis needs posed by these devices, which encompass multiple dies and a specialty package. Besides standard analysis – power, EM/IR, timing – special importance is placed on thermal analysis: “We have a thermal tool called Celsius that can actually analyze the temperature based on finite element analysis as well as computational fluid dynamics, it’s a combination of the two to have high accuracy. But thermal analysis cannot run by itself. You are looking at the temperature conditions on both dies, and you need information from a power analysis tool to understand where the switching is happening. (…) There may be certain hot spots where you may need to move the logic around because it’s going to be heated so much at that point. [Integrity 3D-IC] can even predict the warpage that’s going to happen on multiple levels of dies.” (…) Patwardhan also explained that the platform can run simulations using thermal models to predict the effects of increased temperature on currents. More analysis may be needed for signal integrity in designs using an interposer: “The long routes between two dies have to be SI-aware,” Patwardhan said, “so any SI/PI analysis after extracting the characteristics of the routes is also possible in Integrity 3D-IC. So outside of your standard design closure checks for a 2D SOC, whatever is needed for system-level analysis is available.” That includes “inter-die connectivity analysis or inter-die DRCs through our Pegasus tool. All these tools are embedded inside Integrity 3D-IC for early analysis to give quick feedback, and then they can be run in full sign-off mode as well,” Patwardhan said.

Tackling PVT corner explosion

One of the effects of combining multiple dies in a single package is that the design space to be explored becomes much bigger. Some Integrity 3D-IC features are also addressing this additional challenge. Patwardhan recalled that, at advanced nodes, timing is complex even on a standard 2D SOC, “particularly because of the large number of PVT corners that you have to sign-off on.” Things get even more complicated with 3D ICs: “When you have two dies with synchronous paths in them, or a path going from one die to another die (…) you need to run static time analysis on a very large number of corners,” he said. “For example, if you have a die stack of three dies of nodes 7-nanometer and below, the number of PVT corners can go beyond 3000 actually. It becomes a multi-level problem: how do you manage this much data? How do you fan out the job so that you can solve the delay calculation on such a large amount of data? Is there any redundant data which can be reduced? So in Tempus we have developed actually some significant technology called rapid automated inter-die analysis or RAID, which makes use of a bunch of technologies that were already there in Tempus for advanced mode analysis. One is boundary models: by making boundary models or interface models, you can reduce what’s inside each block and make it a little lighter. Secondly, there is the C-MMC, concurrent multi-mode multi-corner analysis that can be run over multiple CPUs to help with the size of this data. RAID really looks at redundancy, it looks at some smart corner reduction and as a result (…) you can actually bring that large number of corners down to a manageable level and run full STA on it (…). This is a very powerful technology (…) for handling such a complex 3D structure sign-off analysis,” he concluded.

Cadence’s broader 3D IC solution

As explained in the announcement press release – which includes endorsements from imec, Lightelligence, and SaneChips – the new Integrity 3D-IC is part of the broader Cadence 3D-IC solution portfolio, which goes beyond digital and includes system and verification and IP features. The broader solution provides hardware and software co-verification and power analysis of the full system via the Palladium Z2 and Protium X2 platforms. It also provides connectivity via chiplet-based PHY IP. Cadence has prepared several white papers and videos on Integrity 3D-IC and related challenges. These resources can be accessed from this webpage.

Categories: EDACafe Editorial, Video Interview

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