Chips built using 2-nanometer processes will enter volume production in 2025; this, at least, is what we can expect based on the roadmap updates recently provided by both Samsung Foundry and TSMC. For the 2-nanometer node, the South Korean company will adopt its version of the gate-all-around transistor architecture; TSMC is also considering GAA, but has not committed to it yet. More news this week include a 60-billion transistor chip from Alibaba, and a multi-pronged Arm initiative meant to boost the IoT market. But first, a couple of EDA updates.
Ansys adds a charging/discharging simulation solution
Ansys has added EMA3D Charge to its simulation solution portfolio. Developed by Colorado-based Electro Magnetic Applications company, EMA3D Charge enhances predictive accuracy for charging and discharging events that can have an impact on safety for a wide range of electric/electronics products. Leveraging Ansys SpaceClaim, the solution combines CAD import, design and simplification, simulation setup and meshing, and result generalization and visualization into one solver technology. According to Ansys, EMA3D Charge fills a need in a marketplace in which no other simulation product exists, providing a unified end-to-end workflow.
Cadence to speed up ISO 26262 and IEC 61508 certification
Cadence has announced the Cadence Safety Solution, a new offering featuring integrated analog and digital safety flows and engines for faster ISO 26262 and IEC 61508 certification. Targeting safety-critical applications – such as automotive and aerospace – the solution includes a new failure modes, effects, and diagnostic analysis (FMEDA) offering called the Cadence Midas Safety Platform, allowing to perform FMEDA-driven analog and digital verification of safety-critical semiconductors.
