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Archive for September, 2021

Siemens enters the IC power integrity analysis market with a solution for analog, digital and mixed-signal designs of any size

Tuesday, September 28th, 2021

Called mPower, the new software fills an important gap in the EDA market, says Siemens’ Joe Davis


Smaller process geometries make electromigration (EM) and voltage drop (IR) analysis more important than ever for new chip designs, as interconnects and material layers get thinner and thinner. At the same time, smaller geometries mean skyrocketing transistor counts, making detailed EM/IR analysis of a full design a daunting task. On top of that, the growth of sensor-based applications leads to larger analog blocks, where the techniques used in digital blocks to simplify EM/IR analysis are not applicable.

Is the EDA industry keeping pace with the ever-harder requirements of power integrity analysis? According to Siemens, until yesterday the answer was no – and this resulted in some critical pain points. “The largest, most complex analog systems are often sent to manufacturing without a detailed EM/IR analysis; simplifications, subsetting the design, less accurate simulators and other ad hoc methods are used as approximations; lack of detailed EM and IR analysis for large-scale analog circuits puts the whole system at risk,” Siemens maintains in a document on this topic. Identifying those pain points as a market opportunity, Siemens is now introducing its new mPower power integrity software for analog, digital and mixed-signal IC designs. Let’s take a closer look at mPower with the help of Joe Davis – Senior Director at Calibre Interfaces, EM/IR Product Management at Siemens – who recently gave a video interview on this topic to Sanjay Gangal from EDACafe.


AI startups; microLED-based interconnect; silicon nitride photonics; cloud-native automotive software; new solid-state LiDAR

Friday, September 17th, 2021

Artificial Intelligence updates – in terms of new IP and new startup funding – make up a significant part of this week’s news roundup, while other recurring themes include optics/photonics applications and IoT security.

AI updates: Cadence, Deep Vision, Axelera

Cadence has unveiled its Tensilica AI Platform for AI SoC development, including three product families for the low, mid and high end. Built upon the Tensilica DSPs, the Tensilica AI Platform adds a new companion AI neural network engine (NNE) and neural network accelerators (NNAs). The “AI Base” family includes the Tensilica HiFi DSPs and ConnX DSPs, combined with AI instruction-set architecture extensions. The “AI Boost” family adds a companion NNE, initially the Tensilica NNE 110 AI engine, which scales from 64 to 256 GOPS. The “AI Max” family encompasses the Tensilica NNA 1xx AI accelerator family—currently including the Tensilica NNA 110 accelerator and the NNA 120, NNA 140 and NNA 180 multi-core accelerator options—which integrates the AI Base and AI Boost technology. The multi-core NNA accelerators can scale up to 32 TOPS, while future NNA products are targeted to scale to 100s of TOPS. Targeting intelligent sensor, IoT, audio, mobile vision/voice AI and ADAS applications, the Tensilica AI Platform features a common software platform and – according to Cadence – delivers optimal power, performance and area.

Deep Vision has received $35 million in a Series B financing round led by Tiger Global. Deep Vision’s AI processor, named ARA-1, targets camera-based applications such as smart retail, driver-monitoring systems, smart city, drones, and factory automation. The company’s processor also provides natural language processing capabilities.


New fabs; Tesla training system; GaN CMOS; CUDA on Risc-V; Y Combinator startups

Friday, September 10th, 2021

No shortage of interesting news this week – both from the industry and from academia – still it’s worth devoting some space to a Tesla event that took place last month, showing how system-level assembly technologies can make a difference for supercomputers.

Fab and foundry updates: Intel, SMIC, X-Fab, Samsung

Intel’s CEO Pat Gelsinger has reportedly said the company will invest up to €80 billion over the next decade to build new chip fabs in Europe.

According to the Wall Street Journal, SMIC is teaming up with the Shanghai government to build an $8.87 billion chip production line in the city.

Germany-headquartered X-Fab Silicon Foundries is now able to support volume heterogeneous integration via Micro-Transfer Printing (MTP), thanks to a licensing agreement with X-Celeprint. Technologies that may be combined include SOI, GaN, GaAs and InP, as well as MEMS. X-Celeprint’s pick-and-place MTP technology stacks and fans-out ultra-thin dies.

Samsung Electronics has reportedly chosen the city of Taylor, Texas, as the site for its planned $17 billion new chip plant – which will be four times larger than Samsung’s existing fab in Austin. To attract the investment, the city of Taylor has reportedly offered Samsung a $314 million worth of tax breaks for the next ten years.

Source: official City of Taylor website


Google reportedly developing Arm-based PC CPUs; new Risc-V-based datacenter processors; acquisitions

Friday, September 3rd, 2021

News about Arm-based and Risc-V-based processors make up most of the updates this week. As for Risc-V, besides the two startups mentioned below, new adopters include Imagination, which this year is re-entering the CPU market with designs based around the open ISA. Speaking of Arm, according to British newspaper “The Telegraph”, Tesla’s CEO Elon Musk has expressed his opposition to the Nvidia-Arm deal. The Sunday Telegraph also understands that Amazon and Samsung have lodged opposition to the deal with US authorities. As far as EDA is concerned, a very recent update is the resignation of Babak Taheri as chief executive officer of Silvaco and member of the board after two years in the role. The official press release does not provide any explanations for this decision. Let’s now move to the other news.

Translating C++ algorithms to RTL for Microchip FPGA programming

Microchip has added an HLS design workflow. called SmartHLS, to its PolarFire FPGA families that allows C++ algorithms to be directly translated to FPGA-optimized RTL code. The solution is aimed at applications involving edge compute, computer vision and industrial control algorithms that are developed natively in C++ by developers with little or no knowledge of underlying FPGA hardware. The SmartHLS design suite is based on the open-source Eclipse integrated development environment. According to Microchip, the SmartHLS tool requires up to ten times fewer lines of code than an equivalent RTL design.

Google reportedly developing Arm-based CPUs for notebook and tablet PCs

According to Nikkei Asia, Google is developing its own Arm-based CPUs for its notebook and tablet computers which run on the company’s Chrome operating system. Roll out would be planned for 2023. Google is also reportedly ramping up its efforts to build Arm-based mobile processors for its Pixel smartphones and other devices. The company is hiring chip engineers in the US and around the world, including in Israel, India and Taiwan.


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