Cadence’s Vinay Patwardhan explains how designers can tackle the challenges posed by 3D ICs using the new solution recently announced by the company
Placing multiple chips in a single package – either in a 2.5D or in a 3D fashion – is emerging as a viable solution to continue advancing IC performance and functionalities using the currently available process nodes, while keeping die size within lithography reticle limits. However, a package containing two or more dies can be considered as a new type of system, posing new system-level challenges. Existing EDA tools – even the most advanced ones – are mostly meant to address the challenges posed by a single chip and its package; for this reason, the EDA industry is now coming up with new solutions specifically addressing the needs of 2.5D and 3D ICs. Cadence, in particular, has recently announced a new platform called “Integrity 3D-IC”, which it describes as the “industry’s first comprehensive 3D-IC platform for multi-chiplet design and advanced packaging”. To know more about this solution, EDACAfe’s Sanjay Gangal has conducted a video interview with Vinay Patwardhan, Product Management and Group Director, Digital and Signoff Group at Cadence Design Systems.
