New MathWorks release; Arteris IP to go public; compact Risc-V IP; Arm-based servers for AI workloads; new Loihi chip

Catching up on some of the news from the last couple of weeks or so, let’s briefly recall that European Union politicians have started discussing about a plan to support the semiconductor industry in the Old Continent. The President of the European Commission, Ursula von der Leyen, has recently preannounced a European Chips Act. “We need to link together our world-class research, design and testing capacities,” she said in her recent State of the Union speech. “We need to coordinate EU and national investment along the value chain. The aim is to jointly create a state-of-the-art European chip ecosystem, including production. That ensures our security of supply and will develop new markets for ground-breaking European tech. (…) We are world leaders. So let’s be bold again, this time with semi-conductors.” Additional details on the upcoming European Chips Act have been provided by European Commissioner Thierry Breton in this blog post, quoting Imec, CEA-Leti and Fraunhofer as key European assets. “I believe that we should explore setting up a dedicated European Semiconductor Fund,” he wrote. “With the European Chips Act, our tech sovereignty is within reach.”

Copyright European Union, 2021. Photographer: Christophe Licoppe

EDA/IP updates: Cadence, MathWorks, Arteris IP, Bluespec, Sigasi

The new Cadence Helium Virtual and Hybrid Studio is a platform that accelerates the creation of virtual and hybrid prototypes of complex systems. According to Cadence, Helium Studio makes verification with a virtual or hybrid model of the SoC orders of magnitude faster than verification with a pure RTL model, and it also enables early software bring-up before the RTL is available. Natively integrated with the Cadence verification engines – including Palladium Z2, Protium X2 and Xcelium – the new Helium Studio accelerates system development by verifying embedded software/firmware on pure virtual and hybrid configurations even when the RTL is not ready.

MathWorks has introduced Release 2021b of the MATLAB and Simulink product families. New capabilities in MATLAB include code refactoring and block editing, as well as the ability to run Python commands and scripts from MATLAB. Simulink updates enable users to run multiple simulations for different scenarios from the Simulink Editor and to create custom tabs in the Simulink Toolstrip. R2021b also introduces new products called RF PCB Toolbox and Signal Integrity Toolbox.

Arteris IP, the network-on-chip IP supplier, has registered a statement for a proposed Initial Public Offering. The company has applied to list its common stock on the Nasdaq Global Market under the ticker symbol “AIP”.

Risc-V IP supplier Bluespec has released an MCU family of Risc-V processors designed to be implemented on Xilinx FPGAs. The fully Risc-V ISA compliant processor subsystem requires less than 2000 LUTs on Xilinx device. Bluespec’s Risc-V MCU includes a pre-built open-source toolchain and reference designs for the Digilent Arty Artix-7 FPGA Development board.

Belgian EDA vendor Sigasi has added the new Visual Studio Code (VS Code) Extension to its Sigasi Studio product line. VS Code is a cross-platform, customizable development environment that supports numerous languages. According to Sigasi, VS Code combines the simplicity of a source code editor with powerful developer tooling such as smart code completion, navigation, and type time code feedback.

Nvidia and Qualcomm MLPerf results

Nvidia and Qualcomm have interpreted in different ways their respective recent MLPerf inference benchmarks; their respective blog posts are available here and here. As discussed in an interesting EETimes article, benchmark results can be interpreted in different ways, depending on the normalization principle adopted; another controversial aspect is the importance of scoring well across a wide variety of workloads, versus a few specific use cases. An interesting point raised by Nvidia concerns Arm-based servers: “The latest benchmarks show that as a GPU-accelerated platform, Arm-based servers using Ampere Altra CPUs deliver near-equal performance to similarly configured x86-based servers for AI inference jobs.” According to Nvidia, “The latest inference results demonstrate the readiness of Arm-based systems powered by Arm-based CPUs and Nvidia GPUs for tackling a broad array of AI workloads in the data center.”

Second generation of Intel’s neuromorphic chip

Intel has introduced Loihi 2, its second-generation neuromorphic research chip, and Lava, an open-source software framework for developing neuro-inspired applications. Neuromorphic chips use ‘spiking neural networks’ to more closely mimic biological brains. Loihi 2 provides up to 1 million neurons, faster processing and improved energy efficiency. The chip has been fabricated with a pre-production version of the ‘Intel 4’ process, using EUV lithography. The Lava software framework – available for free download on GitHub – runs seamlessly on heterogeneous architectures across conventional and neuromorphic processors. More news includes research from Los Alamos National Laboratory, demonstrating that the backpropagation algorithm – previously believed not to be implementable on neuromorphic architectures – can be realized efficiently on Loihi.

Credit: Intel

Capacity and roadmaps updates: Intel, ASML

Intel has actually started the construction of two new fabs in Arizona, meant to serve both its own manufacturing needs and the recently announced Intel Foundry Services (IFS). The company claims that – when fully operational in 2024 – the new fabs will manufacture Intel’s most advanced process technologies, including “Intel 20A” (where A stands for ångström) featuring the new RibbonFET transistor architecture and PowerVia backside power delivery. In terms of roadmaps, Dutch company ASML is reportedly anticipating that its EUV litho equipment – in the next version with 0.55 numerical aperture – will enable chip makers reach process nodes well beyond the current threshold (2 nanometers) for at least another ten years. The last part of this decade-long path, however, will require the use of double patterning.

Upcoming events

The Vision show is running until October 7^th in Stuttgart, Germany.

Samsung Foundry Forum is taking place as a virtual event from October 6^th to 8^th.

The ValleyML conference on artificial intelligence will run from October 12^th to 14^th.

Silvaco’s “Surge” Virtual Event North America is scheduled for October 14^th.

The ELIV (Electronics In Vehicles) congress will run as an in-person event on October 20^th and 21^st in Bonn, Germany.

The Intel Innovation virtual event is scheduled for October 27^th and 28^th.

Nvidia GTC will be online from November 8^th to 11^th.

Space Tech Expo Europe will run from November 16 to 18 in Bremen, Germany.

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