Risc-V Summit 2020 showcases a growing ecosystem and a wider application spectrum

The virtual event held from December 8 to 10 offered several updates on topics such as core design verification, standard extensions enabling new applications, and open-source EDA tools, with contributions from both the industry and academic research

Almost one quarter (23 percent) of all new IC/ASIC or FPGA projects incorporate a Risc-V processor in their design, according to the 2020 Wilson Research Group functional verification study, a survey – available here and here – commissioned by Mentor. In fact, 2020 has been a year of growth for this open instruction set architecture, as underlined by Calista Redmond, CEO of Risc-V International, in her keynote at this year’s Risc-V Summit. Adoption has grown in all industry segments, including embedded, AI, IoT, HPC etc. Initiatives carried out by Risc-V International in 2020 include ratification of the processor trace specification, a new algorithm that allows to see what instructions a core is executing; a partnership with GlobalPlatform, the standard for secure digital services and devices; new alliances, training programs, and more.

The association also launched the ‘Risc-V Exchange’, with more than 124 Risc-V cores and SoCs and developer boards along with 129 Risc-V software applications and tools. Plans for 2021 include public review for several new standard extensions. Let’s now take a quick look at some of the innovations presented at the Summit. All the papers briefly quoted here can be accessed from the event website.

Risc-V design verification challenges

A key theme at this year’s Summit was the design verification of Risc-V cores, which represents a significant challenge. The regular SoC design flows assume ‘known good’ processor IP and the existence of test benches written for UVM SystemVerilog; while the Risc-V core processor IP can be obtained from a variety of sources and should therefore be verified. But Risc-V flexibility makes processors cores difficult to verify, due to the complex microarchitectures used for achieving PPA targets, many instruction combinations, cache, interrupts, exceptions, and multiple custom extensions. Besides customizations, the Risc-V specification itself continues to evolve – such as in the case of the Risc-V vector extension – adding verification complexity. According to verification tool vendors, the traditional simulation approach is not up to the task as it takes too much time and still can miss critical corner case bugs or the absence of hidden instructions.

New Risc-V verification solutions

Addressing these problems, at least five companies participated in the Summit to showcase their respective verification solutions for Risc-V processors. Axiomise (London, UK) presented a new ‘coverage-driven’ automated formal verification solution that proves compliance testing through formal proofs rather than simulation. The company claims that its push-button solution can achieve three goals: catch bugs, prove bug absence, and sign-off designs. Axiomise used its tools to extensively verify the OpenHW CV32E40P processor. German company OneSpin also contributed to quickly achieve the successful and bug-free delivery of the OpenHW CV32E40P Risc-V core, with its “360 Design Verification” solutions.

Imperas (Oxford, UK) announced enhancements to its Risc-V processor hardware design verification solutions. The new release includes enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, a new free simulator, and a range of Imperas developed Risc-V architectural validation tests for the ratified and soon-to-be-ratified Risc-V ISA extensions.

Indian company Valtrix announced the availability of version 1.9.0 of its Sting design verification platform for Risc-V based implementations. The latest update to Sting includes the support to verify all the recent changes to the Risc-V user and privilege specifications, which include the latest draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the Risc-V hypervisor extension has also been added to enable testing of virtualization use-cases.

Another Indian company, CircuitSutra, addressed the deployment of SystemC-based ESL flows for the design and verification of Risc-V based SoCs.

Widening the Risc-V application spectrum

The Summit offered updates on the different applications that can be addressed by Risc-V cores, thanks to new standard extensions and a growing software ecosystem. Targeting high end data center and enterprise applications, CHIPS Alliance announced it plans to work with Risc-V International to standardize on the OmniXtend cache-coherent memory fabric developed by Western Digital, which allows heterogenous systems that use TileLink cache-coherence protocol to share the memory coherently. CHIPS Alliance is an organization which develops open-source IP cores, hosted by the Linux Foundation.

As far as IoT applications are concerned, Green Hills Software announced the availability of its safety certifiable µ-velOSity real-time operating system for Risc-V. Along with middleware, hardware JTAG probe, and Green Hills’ Multi development tools, the RTOS provides a single integrated development environment that targets debug and optimization of heterogeneous processor SoC designs where the Risc-V core coexists with Arm or Intel CPUs.

Also targeting IoT application is the Tiny-FPU presented by Swiss technology institute ETH Zurich. The IEEE-754-2008-compliant Risc-V FPU is optimized for circuit area, while offering higher performance compared to the alternative solution of using software emulation to perform floating point arithmetic.

Virtualization in embedded applications was the subject of a presentation from University of Minho (Portugal). Waiting for the Risc-V hypervisor extension specification draft to be ratified, the researchers have ported an existing open-source static partitioning hypervisor – called Bao – to Risc-V.

Space application were also addressed. Barcelona Supercomputing described the De-RISC project, whose objective is to produce the first Risc-V multicore space-certifiable platform of an entirely European development. The De-Risc platform includes the XtratuM hypervisor and LithOS RTOS by Spanish company fentISS, and Gaisler’s NOEL-V based MPSoC.

New Risc-V processors

Most vendors of Risc-V chips and IP cores obviously participated in the Summit, along with companies that develop Risc-V-based devices for their own products. Cobham Gaisler, for example, presented its NOEL-V processor family and more specifically the HPP64, a 64-bit high-performance in-order dual-issue processor.

Seagate announced that it has designed two Risc-V-based processors for its storage devices, one of them being performance-optimized while the other is area-optimized. The high-performance processor has already been built and demonstrated as functional in hard disk drives, paving the way for finer positioning by implementation of advanced servo (motion control) algorithms. The area-optimized core has been designed and is in the process of being built. It can execute security-sensitive edge computational operations, including next-generation post-quantum cryptography. According to Seagate, introducing Risc-V to storage devices enables massive parallel ‘computational storage’ solutions.

A growing open-source design flow

The Risc-V Summit is also a good observation point on the growing ecosystem of open-source EDA tools. Antmicro (a company based in Sweden and Poland) presented a number of efforts aimed at building an open-source SystemVerilog ecosystem of scalable and reusable solutions – which could clearly be used to create and test Risc-V cores, too. As explained by the speakers, most available tools for working with SystemVerilog are proprietary, and there is a range of open-source Risc-V cores and IPs implemented in SystemVerilog which cannot yet be built with open-source tools. Antmicro is also working on other open-source tools together with Google, Western Digital and CHIPS Alliance.

Tim Ansell from Google presented the fully open source manufacturable PDK for a 130nm process developed by Google and US-based foundry SkyWater, part of an effort to enable future chips to be open “all the way down to the transistor”. The effort includes a new open-source free ‘shuttle program’ (a multi project wafer) offered by Google and efabless (San Jose, CA).

Savings obtained through the use of an open-source ecosystem and tools obviously reflect in a lower cost of chip development. At the Summit, Berkeley-based Intensivate (which produces accelerator cards for data centers) described its experience in developing the first commercial Risc-V “cluster CPU”, delivering a commercially viable chip, in a 12nm process node at less than $10M. The company used open-source EDA tools developed at Berkeley University: Rocket-Chip RTL from Chipyard, FireSim FPGA emulation system, and the Chisel hardware description language.

Open-source development tools for AI applications

The open-source ecosystem being built around Risc-V obviously includes development tools for AI applications. This theme was addressed at the Summit with a session titled “Building an Open Edge Machine Learning Ecosystem with Risc-V, Zephyr, TensorFlow Lite Micro and Renode.” Among the papers concerning this theme, researchers from University of Bologna, Italy, presented a fully open-source flow (“from Python to silicon”) to deploy DNNs on top of systems based on the Risc-V based PULP platform, such as GreenWaves Technologies GAP-8. The PULP (Parallel Ultra-Low-Power) platform is a joint project from ETH Zürich and University of Bologna.

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