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 EDACafe Editorial

Archive for November, 2020

IC market forecasts; new edge AI chips; automotive software

Monday, November 30th, 2020

The so-called ‘semiconductor renaissance’ is tightly related to the artificial intelligence boom, so this week the latest IC market growth figures fit well with the updates about new edge AI chips from well-funded startups. Automotive software is also making news, along with some last-minute additions to the virtual events calendar.

Intel still number one semiconductor supplier in 2020

According to the latest forecast from market research firm IC Insights, Intel will keep its number one semiconductor supplier ranking in 2020. As noted by the analysts, this year the Covid-19 pandemic spurred an acceleration of the worldwide digital transformation resulting in a robust semiconductor market growth. In total, the top-15 semiconductor companies’ sales are forecast to jump by 13% in 2020 compared to 2019. In contrast, in 2019 the top-15 semiconductor suppliers registered a collective 15% decline in sales. IC Insights expects two new entrants into the top-15 semiconductor sales ranking for this year: MediaTek and AMD. Forecasted sales increases for these companies are 35% and 41%, respectively. Peculiar to this list is the inclusion of Apple – which uses its chips only in its own products – and of foundries like TSMC – which mean that some sales are double counted.


Intel FPGA news; Ferroelectric Memory; Micron’s 176-layer NAND; TSMC’s Phoenix fab; Tesla security issue

Monday, November 23rd, 2020

Step-by-step instructions on how to steal a Tesla are probably this week’s most curious news, even accompanied by a video (by the way: the security flaw has already been fixed by Tesla). But first, the usual weekly news summary.

PSS 2.0 draft available for public review

Accellera has announced the availability of the Portable Test and Stimulus Draft Standard 2.0 (PSS) for public review. New major features intend to improve the usability of the standard and expand its portability and flexibility to a broader class of verification challenges. Public review was opened on November 18 and will close on December 18, 2020.


Reactions to AMD-Xilinx deal; more acquisitions; upcoming events

Monday, November 16th, 2020

Acquisitions make up most part of this week’s article. Catching up on some of the news from the last thirty days, the AMD-Xilinx deal inevitably stands out – clearly no longer as a fresh update, but as a topic that deserves some reflections. We will therefore take a look at some of the comments that have been published by the media. Coincidentally, several more acquisitions were announced over the past few weeks – clearly much smaller, but still significant in their respective markets.

AMD-Xilinx deal: some comments from the media

With the acquisition of Xilinx, AMD hopes to create “the industry’s High Performance Computing leader”. The future scenario for HPC silicon, therefore, could be characterized by three major competitors: Nvidia (with the recent addition of Arm), Intel (which bought Altera in 2015), and the AMD-Xilinx combination. Sally Ward-Foxton on EETimes asks a question that is key to figure out the future competitive landscape: “Is AMD trying to build a complete data center computing platform, similar to what Nvidia is trying to do with Arm?” She also observes that “Nvidia has plans to combine Mellanox’ SmartNICs with Arm CPU accelerators and VLIW acceleration blocks to make what it calls a DPU (…). AMD doesn’t have anything in this area, but Xilinx does — a SmartNIC platform based on its FPGAs was launched this spring.” Commenting the new scenario, Kris Kachris on SemiWiki anticipates less freedom of choice for customers: “We are moving on the era of Heterogeneous Data Processing Platforms where computing platforms will include SmartNICs, multi-core processors and hardware accelerators and the user will have to select a complete solution instead of mix-and-match. Intel, AMD and Nvidia will offer complete computing platforms with their own proprietary accelerators and SmartNICs. (…) the option to select the best of each world will not be feasible any more or at least it will be more challenging.”


New testing challenges take center stage at the International Test Conference 2020

Tuesday, November 10th, 2020

Smaller process geometries, multibillion-transistor designs, zero-defect requirements, emerging memories, new security threats: technology advancements and evolving application constraints make chip testing increasingly challenging and increasingly important. Researchers around the world, in the semiconductor industry and in the academia, struggle to overcome these new challenges – aiming to ensure effective chip testing while preserving the best possible PPA results and optimizing the use of testing resources. Every year, the International Test Conference offers a wide selection of some of the best research works in this area, and the 2020 edition – which took place as a virtual event from November 3rd to 5th, sponsored by IEEE and the IEEE Philadelphia Section – was no exception. This week, EDACafe quickly browses through the proceedings of ITC 2020, peeking into a few sample papers just to give a sense of the new challenges confronting test engineers, and a taste of the new solutions that are being proposed.


Linley Fall Processor Conference 2020 – Part Two

Tuesday, November 3rd, 2020

Last week, EDACafe provided a quick overview of some of the presentations which were given during the first part of this year’s Linley Fall Processor Conference, from October 20 to 22. This week we complete our coverage of the virtual event – organized by The Linley Group – by quickly summarizing some of the presentations which were given during the second part of the conference, from October 27 to 29. No shortage of innovations in this period, which is also characterized by big deals (Nvidia-Arm and AMD-Xilinx) in the processor industry.

TinyML chip requirements: the Google point of view

The second part of the conference was kicked off by a keynote from Peter Warden, Technical Lead of the TensorFlow Micro open source framework at Google. Warden summarized the requirements that chip vendors will need to satisfy to make the vision of TinyML come true. He foresees a future of hundreds of billions of “peel-and-stick” sensors placed on everyday objects – used for industrial monitoring, environmental monitoring, building automation, agricultural and wildlife use cases etc. – all of them capable of full-vocabulary speech recognition and/or person and gesture recognition.

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