The virtual event held from December 8 to 10 offered several updates on topics such as core design verification, standard extensions enabling new applications, and open-source EDA tools, with contributions from both the industry and academic research
Almost one quarter (23 percent) of all new IC/ASIC or FPGA projects incorporate a Risc-V processor in their design, according to the 2020 Wilson Research Group functional verification study, a survey – available here and here – commissioned by Mentor. In fact, 2020 has been a year of growth for this open instruction set architecture, as underlined by Calista Redmond, CEO of Risc-V International, in her keynote at this year’s Risc-V Summit. Adoption has grown in all industry segments, including embedded, AI, IoT, HPC etc. Initiatives carried out by Risc-V International in 2020 include ratification of the processor trace specification, a new algorithm that allows to see what instructions a core is executing; a partnership with GlobalPlatform, the standard for secure digital services and devices; new alliances, training programs, and more.
The association also launched the ‘Risc-V Exchange’, with more than 124 Risc-V cores and SoCs and developer boards along with 129 Risc-V software applications and tools. Plans for 2021 include public review for several new standard extensions. Let’s now take a quick look at some of the innovations presented at the Summit. All the papers briefly quoted here can be accessed from the event website.
