Several interesting announcements are making news this week, both from EDA-IP vendors addressing the requirements of next generation chips, and from chipmakers targeting advanced automotive, consumer and industrial applications.
Addressing the IR drop analysis issues
Due to the effects of highly resistive lower metal layers, one of the challenges posed by the design of advanced high-speed chips at 7 nanometers and below concerns the IR drop analysis. In these designs, timing is dependent on IR drop and vice-versa, making IR drop analysis a key signoff technology. To address these issues, Cadence has integrated two of its preexisting products: the Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution. According to Cadence, the resulting tool – called Tempus Power Integrity Solution – allows to significantly lower IR drop design margins without sacrificing signoff quality, thus improving power and area. Early use cases cited by Cadence demonstrated that the new solution correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Other benefits include a proprietary vectorless-based algorithm to identify critical paths most likely impacted by IR drop.
