Posts Tagged ‘New Electronics’
Thursday, February 9th, 2012
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com No Comments »
Monday, January 30th, 2012
The main technical breakthroughs we can expect this year will probably revolve around double patterning in lithography as EDA companies try to optimize the technique for density and performance. And it will probably have knock-on effects way up in the design flow, forcing designers to adopt much more regular designs. But, unless EUV sees a major breakthrough, double and further levels of multiple patterning is something people will need to get used to.
Regularity is likely to become a feature of low-power design as well. Although it hurts effective density, the drive to cut power consumption will see much more use made of on-chip redundancy – we’ve already seen some of that in the nVidia Tegra 3 and the ARM Big.Little initiative. We could see those techniques begin to extend into ultralow power circuits using near or subthreshold devices as engineers discover how to model circuits effectively and recover lost performance at very low voltages. Some of these techniques will also help reinvigorate older processes – using better EDA to trim power consumption instead of relying primarily on process changes to deliver better energy efficiency.
Chris Edwards
Technology writer: Engineering & Technology, New Electronics, Low-Power Design Blog, Tech Design Forums
Tags: 2012, ARM, circuit-design, EDA, EDA & IP, Electronic Design Automation, Engineering & Technology, EUV, Lee PR, low power, Low-Power Design Blog, multiple patterning, New Electronics, NVIDIA, semiconductors, Tech Design Forums, Tegra 3, www.leepr.com No Comments »
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