Posts Tagged ‘FPGA’
Thursday, February 9th, 2012
To finish off our series of predictions, I would like to point you to another series of interesting and informative prophesies. Click on the following topics to see these predictions collected by Brian Bailey, Editor of EDA DesignLine.
Industry Trends
Tools
ESL
IP and Physical Design
The Bold Prediction for EDA
A big THANK YOU from Ed & me (Liz) to all who shared their eye opening predictions with us. Click on their names to see their predictions. Mike Gianfagna, Karen Bartleson, Paul McLellan, Jens Andersen, Bob Smith, Steve Schulz, Mathias Silvant, Herb Reiter, Max Maxfield, Chris Edwards, John Barr.
Only time will tell……
 The Persistence of Memory, 1931, Salvador Dali
Tags: 2.5D, 2012, 3D, 3D stacked die, Ansys, Atrenta, Cadence, Dassault, Double Patterning, EDA, EDA & IP, eda 2 asic Consulting, EDA DesignLine, EDA360, EdXact, Electronic Design Automation, Engineering & Technology, FPGA, Invarian, investment, IP, Lee PR, Lithography, low power, Low Power Design, Low-Power Design Blog, Magma, Maxfield High-Tech Consulting, Mentor, Needham, New Electronics, Programmable Logic, Programmable Logic DesignLine, publishing, Semi-wiki.com, Semiconductor IP, semiconductors, Si2, SoC, SoC Realization, social media, software, Standards, Synopsys, System on Chip, Tech Design Forum, textbooks, www.leepr.com
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Wednesday, January 25th, 2012
On the ASIC/SoC side of the fence: Reducing power consumption is becoming increasingly important — I anticipate that this is the year that power will finally come to the forefront of EDA tools — I know that they optimize for power now, but largely as a second thought — like synthesis, for example, optimizes first for area and timing and then for power — I think we’ll see a move to optimize for power as a primary consideration.
On the FPGA side of the fence: As we move to the 28nm node and below, radiation is increasingly of concern with regard to electronic devices. It’s no longer just of interest for aerospace applications — at these low device geometries, radiation can affect chips in terrestrial applications. FPGAs are particularly susceptible because in addition to their normal logic and registers and memory cells they also have configuration cells. In the past, the only radiation-tolerant FPGAs were antifuse based — but these are only one-time-programmable (OTP) and trail the leading edge technology node by one or two generations. SRAM-based FPGAs offer many advantages in terms of reconfigurability and being at the leading edge of technology, but they are more susceptible to radiation events in their configuration cells. My prediction is that we will see more and more efforts from FPGA chip vendors and EDA tool vendors with regard to creating radiation-tolerant designs.
On the personal side of the fence: I predict that people will come to realize that what the world needs is a book about creating radiation-tolerant electronic designs that can be read and understood by folks who DO NOT have a PhD in nuclear physics — a book that is of interest to the people who design silicon chips (both analog and digital), the people who create EDA tools, the companies who manufacture the chips, and even software engineers (have you heard of “radiation tolerant software”?). I further predict that someone will finally realize that I am the best person to write this book and will approach me with a really great sponsorship deal that will bring tears of delight to my eyes 🙂
Clive “Max” Maxfield
Maxfield High-Tech Consulting
Editor, Programmable Logic DesignLine, EE Times
www.CliveMaxfield.com
Tags: 2012, ASIC, EDA, EDA & IP, EE Times, Electronic Design Automation, FPGA, Lee PR, low power, Maxfield High-Tech Consulting, Programmable Logic, Programmable Logic DesignLine, publishing, semiconductors, SoC, software, SRAM, System on Chip, textbooks, www.leepr.com
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Tuesday, September 7th, 2010
This is the 2nd part of my interview with Joe Gianelli, VP of Marketing and Business Development of the new start up…..InPA Systems.
Liz: Joe, can you give us a little bit of background on InPA’s founders, Thomas Huang and Michael Chang?
Joe: Both Tom and Michael are longtime EDA entrepreneurs, having founded a number of startups, bringing to InPA a wealth of expertise in logic emulation, rapid prototyping and RTL verification.
Tom is probably best known as a co-founder and CTO of PiE Design Systems. He continued on with Quickturn when it acquired PiE. He was also EVP and CTO of Aptix, a rapid prototyping company, and founded several other companies in the emulation and ATE areas.
Michael was a co-founder, CEO and president of Verplex, a formal verification company that was acquired by Cadence. At Cadence he served as VP and GM of the formal verification group. Michael also founded Checklogic, which was acquired by Mentor.
Liz: And how about yourself? What is your background?
Joe: I was involved in the successful launch and acquisition of Taray just before joining InPA. I have spent my entire career in EDA, making the rounds from Synopsys to Epic Design to Meta Software and to Cadence. I was at Synplicity for 10 years, where I was VP of Business Development.
Liz: That’s an impressive combination of experience and expertise that you all bring to the table. Did I notice some high profile names on your advisory board?
Joe: You sure did! Bernie Aronson, from Epic, Synplicity, Kilopass; Michel Courtoy, from Certess; Sean Torsney of Verplex, and Kazuyuki Kawauchi from Fujitsu.
Liz: So what are your initial target markets?
Joe: SoC projects using FPGA prototype systems to verfy and validate their SoC’s.. Right now, we’re focusing on North America and the major Asian markets. We’ll obviously be going into Europe shortly.
Liz: When can we expect to see your first product?
Joe: This really depends on the success of our beta sites, could be as early as late Q4.
Liz: Thank you, Joe, for giving us a little insight (or should I say visibility?) into InPA Systems. I’m sure we’ll be hearing more and more about InPA and Active Debug in the near future.
 Tom Huang  Michael Chang
Tags: EDA, FPGA, InPA, InPA Systems, rapid prototyping
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Wednesday, August 25th, 2010
Liz Massingill interviews InPA’s Joe Gianelli
This month, a new company announced its entrance into the rapid prototyping space. It goes by the name of InPA Systems. I was lucky enough to be able to grab a few minutes with its VP of Marketing and Business Development, Joe Gianelli, in order to learn a little bit about this new start up, its exciting new technology and how it could impact the future of rapid prototyping.
 Joe Gianelli
Liz: InPA….not an obvious name. What does it stand for?
Joe: Yeah, that’s an obvious question. It stands for integrated prototype automation, which are the characteristics of the technology we bring to the market.
So what InPA Systems is integrating is the RTL simulation and FPGA prototyping environments and automating a critical portion of the “bring up” that verifies that the mapping of the RTL code into the multiple FPGAs correlates to the original RTL code.
Liz: So InPA is in the rapid prototyping area, a segment that’s been around for, what, 20 years? What do you bring to the market that’s new?
Joe: InPA’s mission is to more fully harness the power of today’s FPGA rapid prototyping systems. Our most noteworthy technological capability is bringing debug visibility to users – who used to have to fly blind.
Basically, Tom (Huang) and Michael (Chang) saw the need for a more complete rapid prototype environment that integrated today’s RTL verification and rapid prototype environments with better visibility.
Liz: So technically, how does this work?
Joe: Without getting into a technical schpiel, InPA Systems integrates the RTL code and FPGA prototype environment so that engineers can debug in their RTL code while accessing their captured faulty conditions with full visibility. The automation here is to cross-link the RTL code with the captured faulty condition and to expand full signal visibility around the faulty condition.
We’re also enabling full system debug. This is when engineers are integrating the software and hardware design components enabling engineers to catch issues easier when integrating both HW/SW in the FPGA prototype environment. The automation here enables full system debug with “active debug” technology to dynamically control HW and to cross-trigger between FPGAs.
And finally, we’re automating the full capture of faulty conditions across multiple FPGAs. Today, engineers must capture and debug one FPGA at a time.
Liz: That’s got to be key! Why is it important or noteworthy to integrate and automate this?
Joe: It’s extremely tedious and difficult to isolate a hardware problem when it spans RTL code over multiple FPGAs. Giving the engineer the ability to fully capture the faulty scenario leads to much quicker isolation of the actual problem.
Liz: What does this new technology offer to the user that he or she hasn’t been able to accomplish up until now?
Joe: Right now, engineers probe around in the dark looking for problems in the hardware, one FPGA at a time. We give them the tools to explore various scenarios without having to recompile FPGA place and route…this is a real pain for engineers today. And we give them full visibility around their problem, making it easier to detect and fix.
Liz: What does “active debug” mean?
Joe: It’s allowing the engineer to remain active in the debug process; forcing certain circuit states, capturing data at speed, analyzing the data, and essentially remaining active in the debug process as opposed to probing around in the dark and waiting for another FPGA P&R iteration. What we call Active Debug is a combination of technology and methodology that increases the productivity of engineers who are integrating hardware and software and validating in-system with a rapid prototype .
Liz: So it’s an answer to the old debug visibility problem, right?
Joe: You got it.
Liz: So I have to ask, how is it different from existing debug? Passive debug, is it?
Joe: Yes. As most current systems use the passive debug approach, they only probe the circuit looking for possible problems with limited visibility, which doesn’t allow the user to dynamically create different conditions in the circuit that allow for testing of those conditions while running in the FPGAs.
In contrast, active debug allows the user to force various conditions in the circuit, capture over multiple FPGAs, analyze in a user friendly simulation environment, while reducing the number of FPGA P&R iterations.
Liz: Why is it important to debug in your “active” mode?
Joe: One of the biggest challenges of the SoC design team is debugging problems when integrating SW and HW together. Today, most SoC design teams are integrating their SW and HW on FPGA prototype systems and using the debug tools from the FPGA vendors which were not architected to debug large SoC designs over many multiple FPGAs. Consequently, engineers are not very productive using these tools as they search in the dark, one FPGA at a time, with limited visibility. Allowing engineers to become more “active” in their debug process moves them closer to isolating the bug much faster. It’s really allowing them to do their jobs much more efficiently.
Liz: I’m trying to hone in on the visibility function InPA brings to designers. What do you mean by “visibility” and how is that different from current prototyping methods again?
Joe: Visibility is really two things. First, it’s allowing engineers to capture their faulty conditions over multiple FPGAs as opposed to one FPGA at a time. This gives them much greater visibility into the potential problem. Secondly, our technology expands all the signals in the captured scenario giving engineers full signal visibility.
Part 2 of this interview will air on September 6.
Tags: EDA, FPGA, InPA, InPA Systems, prototyping, rapid prototyping
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Thursday, December 3rd, 2009
(Liz Massingill concludes her conversation with blogger Dan Nenni.)
Liz: I know that bloggers don’t want press releases. They want to talk about trends.
Dan: Every blogger has an agenda. I blog about experiences, companies, and technologies that I know, positive and negative trends that I see. I do blogs on TSMC and the other foundries all the time. My agenda there is to let people know that if you are part of the semiconductor design enablement supply chain you need to be very close to the foundries. When bloggers are really product specific, like some corporate bloggers are, it just looks like something from a company–a public notice. But if they talk about market trends and put their personality and their experiences into it, then it becomes interesting.
Liz: How long will it take the industry to be more social media savvy?
Dan: I don’t know if it will be in my professional lifetime or not? But if you look at it, we’re raising the Social Media Generation— Facebook, MySpace, and Twitter.
I have 4 kids, and all of them are really into it. They’re prolific texters–they communicate with their thumbs. When those people get jobs and become our target market you’re going to have to market to them, right?
Unfortunately, most people our age aren’t that savvy. I picked it up early because I have kids. I’m involved with them and their social media habits. I have 6 cell phones and I didn’t have texting because my kids were starting to drive. My Verizon bill was thousands of minutes. They begged me for texting so I got the unlimited plan. My calling minutes went from thousands to a few hundred. The thing is that they don’t communicate by phone, that’s just not the way their generation wants to communicate, period. I turned texting off on my phone to eliminate yet another distraction.
My attitude was that if you want to talk to me, call or email me. And they don’t (laughs). So those are the people we are bringing up now, the thumb generation, and this is happening in America, China, Iran, everywhere.
If you don’t GET social media, you are going to be at a significant disadvantage in business and life in general. I think we’re coming close on the business side. Companies should start now or they won’t be competitive. That’s why I’m an evangelist for social media because it’s THE most cost effective demand creation vehicle.
In our business, the average shelf life of a marketing message is like a loaf of bread, things/specs change so quickly. You need to refresh your message in a cost effective manner on a monthly basis; and that is Social Media.
Liz: There’s always press releases (laughs)
Dan: People don’t care. No offense but traditional PR does not work the way it used to.
Liz: What about print media vs. online media? Aren’t there many people who would rather read a hard copy than have to remember to go read something online?
Dan: I don’t read the newspaper anymore because by the time I get it, it’s old news, so I use Google Reader. I’m on my laptop anyway doing email, watching videos, etc… How much time do people spend on their computers? 50% of your day? Some people even eat in front of their computers.
(Liz raises hand sheepishly.)
Dan: So where are you going to get your news? In the newspaper, the only thing I read is the comics, the Jumble, Dear Abby, Safeway ads (I do the shopping). Nothing else, and I hate getting news print ink all over the place. Seriously, smudge proof ink, how hard is that?
Liz: What is it you want or don’t want from PR people?
Dan: I want PR people to embrace social media and make it their own, simple as that. Bloggers are easy to work with. Bloggers want blog views, views are empowering and feed our massive egos. You have no idea what a burden it is to support a massive ego, so anything you can do to help get blog views is greatly appreciated. Invite us to functions, buy us lunch, integrate Social Media into your business model, just don’t send us press releases!
Liz: Jim Hogan threw down this gauntlet in his recent presentation at ICCAD….that EDA is complacent. We’ve talked a bit today about how there doesn’t seem to be much of an interest in EDA but a lot of interest in foundries. How do you think that relates? Do you agree with Jim’s assertion?
Dan: Yes EDA is complacent, I agree with Jim. My audience is definitely interested in the foundries, also semiconductor IP and design services. So why not EDA? One theory is that EDA does not share the risks and rewards of semiconductor design, so EDA is not invested in/with the customer. EDA software is licensed upfront and gets paid whether the customer is successful or not.
Foundries, IP companies, and design services are more success oriented and get paid on volume silicon shipments. Based on that, customers view EDA companies differently, especially when licenses expire and their design has not taped-out yet!
Liz: How do FPGAs figure into the picture?
Dan: FPGAs are a big factor in the decline of EDA, and everybody knows it. I think that is a relevant point if you are talking about the state of EDA. FPGA design starts are going up and ASIC/EDA design starts are going down. FPGA’s are also success based with volume silicon shipments being the big payday for all, sound familiar? 😉
Liz: What do you think the trend for EDA will be for the next 10 years?
Dan: EDA is going to be interesting the next few years, and I am happy to be a part of it. I would like to send a strong but positive message: Change is coming. If EDA does not embrace this change, it’s going to be a very costly experience. Success based business models are key, working closely with the foundries is key, being an accretive member of the semiconductor design enablement community is the cure for EDA complacency. Believe it.
– end –
Tags: Dan Nenni, EDA, EDA complacency, foundries, FPGA, Jim Hogan, leepr.com/home/html, TSMC
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Tuesday, November 3rd, 2009
Jim Hogan and Paul McLellan gave an ICCAD audience their take on what’s ahead (over the next decade) for EDA.
They ended the session with the gauntlet statement: “EDA is too complacent.” And curiously, not one person responded.
If you’re interested in what Jim and Paul presented (and what the responses have been from industry bloggers and reporters), click on the Lee PR link here: http://leepr.com/Home.html
Tags: chip desgn, EDA, EDA is too complacent, FPGA, future of systems design, http://www.si2.org/?page=1089, Jim Hogan, Lee PR, Lee Public Relations, Paul McLellan, silicon platforms, software signoff, systems design, www.leepr.com
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