Gary, along with Mike Gianfagna of Atrenta and Jason Andrews and Frank Schirrmeister of Cadence, will examine the evolution of ESL over the past few years and share the breakthroughs that have occurred in the flow.
When is it?
11:00-11:45 am PDT
Monday, August 19, 2013
Gary will be recognizing the industry’s “ESL Heroes.” Want to know what an ESL Hero is? Tune in Monday to find out.
Before the summer ends and the summer blockbuster movies and DAC become a distant memory (still shaking my head over The Lone Ranger’s flop), let me just share Mike Gianfagna’s vision for next summer’s blockbuster.
It’s a tad more like Terminator 2 than the masked man and Tonto. And it may not be too far from reality – that’s what’s exciting…..and scary.
Of course it’s about the semiconductor supply chain and how it might affect our lives in the future.
For those of you who were unable to attend the big 50th DAC party, or you just missed the intro to Asleep at the Wheel, you might find this little video entertaining.
It’s a video of Cowboy Ajoy and Ranger Rhines (aka Ajoy Bose, CEO of Atrenta and Wally Rhines, CEO of Mentor), cutting it up on the Austin City Limits stage to kick off Kickin’ it up in Austin.
In the following video, Warren Savage, CEO of IPextreme, talks with Mike Gianfagna, VP of Corporate Marketing at Atrenta, about collaboration – with TSMC and the Constellations partners.
Mike’s dream is for “a vibrant industry with a well-defined quality metric.”
KNTV, the Bay Area NBC affiliate, covered a story this past Friday on how Silicon Valley is the nation’s mecca for startups. KNTV reporter Scott Budman contends that Silicon Valley is stretching its borders north to Oakland. Really?
According to a survey conducted by the National Venture Capital Association, San Francisco is the nation’s hottest city for tech startups, with San Jose coming in second. Oakland is ranked at No. 11.
As part of this story, Budman interviews San Jose EDA firm, Atrenta, pointing to Atrenta as a typical Silicon Valley startup.
With less than 3 weeks away until DAC’13, Liz and I asked Warren Savage about IPextreme’s and Constellations’ planned presence there. Warren is not only founder and CEO of IPextreme, but also head of the IP consortium, Constellations.
We caught up with Warren recently, and Mike Gianfagna, VP of Corporate Marketing at Atrenta (Atrenta is a Constellations partner), happened to be there. So, the two of them let us in on what Constellations would be up to at DAC.
Liz: Warren, what play does IP have at DAC this year?
Warren Savage President and CEO IPextreme
Warren: Change is slow, but IPextreme and Constellations are happy to report change is afoot and our workshop at DAC serves as a prime example of this. Together with TSMC and our Constellations partners Atrenta and Sonics, we are pleased to present “Driving Quality to the Desktop of the DAC Engineer” on Sunday, June 2 from 1:00 to 5:00 PM. This workshop showcases a foundry, two IP companies, and an EDA company working together—exactly as we do every day.
Why, then, is this the first DAC workshop of its kind? Why have the ties binding us together in the semiconductor ecosystem not been highlighted before? Perhaps the old saying, “If all you have is a hammer, everything looks like a nail,” is the only explanation. At the end of the day, our customers need all of us – both IP providers and EDA vendors. We owe it to them not only to recognize that, but also to make their lives easier by working together.
These two trend setters share their opinions on the BIG DACthemes in 2013.
I see two related trends:
1) More signoff activity earlier in the design flow
2) More focus on IP quality and usability
Both of these trends represent a maturing of design tools and business models. Because of the tremendous complexity that sub-20 nm design brings, it becomes more important to get the design right as early as possible. The tools are maturing in the earlier stages, and more designers are demanding clean reports, or sign-off level quality audits as a result. This is helping to reduce schedule delays and design costs – good for the industry.
Semiconductor IP is also maturing – both use models and business models. There is a growing focus on reporting delivered quality and robustness. This will allow IP providers that deliver the best IP to flourish. Also good for the industry. We’ll see an increase in conversations about IP providers collaborating with the rest of the ecosystem at DAC. Another good trend.
In my last blog, Harrison Beasley shared his views on stale IP. This week we hear from Manoj Bhatnagar, Senior Director, Field Delivery and Support at Atrenta.
Liz: Manoj, what is stale IP?
Manoj:An IP may become stale because either its specifications have changed (e.g., USB 1.0 vs. 2.0 vs. 3.0) or there is a better implementation available (e.g., a graphics core is now running at 800Mhz instead of 500Mhz). Typically, people will use the latest version, and the older versions are no longer used. So the stale IPs in this case will die a natural death. What is more challenging, however, is a specific IP developed for a specific project and, over time, no other project used it. So the IP becomes stale. Most of my answers will apply to this type of stale IP.
Liz: What’s so bad about it?
Manoj: The main issue with a stale IP is the fact that nobody really knows the details about it. If I were to use that IP, I would be putting my design at risk because I am now adding some logic to my design for which I don’t have all the information and can’t find anyone who can provide that information either.
Liz: How do we prevent it from being stale?
Manoj: One of the key things that can be done to prevent IP from going stale is to document the IP. I don’t know how many people still remember the TTL datasheets but when you looked at the datasheet, you got complete visibility into what that component did. The same concept can be applied to present day IPs, where you document various characteristics of the IP. For a hard IP, this may be the timing characteristics, physical profile, etc. while for a soft IP this may be timing constraints, clock domain information, testability profile and power profile.
What are the challenges in managing semiconductor IP?
How can we solve IP reuse integration?
If you’d like to know the answers to these questions and others, check out this presentation by Michael Johnson of Atrenta from the Constellations 2012 conference.
Johnson succinctly defines soft IP quality and proposes a way for the industry to get to a soft IP quality standard.
