Posts Tagged ‘verification’
Friday, August 11th, 2017
 FPGA Design Verification Challenge
The FPGA design and verification “ecosystem” changes rapidly to keep pace with the fast growing size of FPGA devices. The largest Xilinx Virtex UltraSCALE chips provide 4.4 Million logic cells or using another metric 50 million equivalent gate count.
To enable efficient design process for Virtex-7 and newer UltraSCALE FPGAs, Xilinx provides software called Vivado Design Suite. Besides supporting a classical HDL design flow, it also provides system level design tools like IP Integrator, System Generator or even High Level Synthesis, that are very convenient for designing large and complex designs.
Verification has always taken a significant share of the project schedule with HDL simulation being the main stage of that process. With such big designs however, even the fastest simulators would spend hours in simulation tasks.
Simulation Acceleration with HES-DVM™
Aldec’s HES-DVM bridges this gap enabling accelerated simulation with the design running in the FPGA and the testbench in the simulator.
Aldec has been providing HES™ – Hardware Emulation Solutions since 2001. During that time the HES evolved to address the most sophisticated design requirements and fulfill customers’ requirements. Thus, simulation acceleration is only one example of how HES can be used with other applications being hybrid co-emulation, in circuit emulation, and physical prototyping.
With simulation acceleration the user can move any synthesizable module from simulator to the FPGA thus offload some processing from the HDL simulator. Typically, an entire design is implemented in HES board and the simulator only executes the testbench.
Figure 1: Signal-level simulation acceleration
The HES boards are seamlessly integrated with the simulator with PCI Express x8 physical connection to the host workstation. The HES-DVM provides co-simulation interfaces for Aldec’s Riviera-PRO and Active-HDL simulators but also for other 3rd party simulators. It can be used both in Linux and Windows operating systems with all required PCIe drivers and interfaces working out of the box.
The DVM tool automates the process of design compilation and implementation for HES boards. It generates all necessary scripts and configuration files to run simulation acceleration in a given HES board but also brings many useful debugging features. Despite running your design in FPGA hardware you can keep simulation level visibility with an RTL View of all internal probes.
Figure 2: Design setup flow for acceleration using DVM™
Acceleration Benchmark
MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.How much acceleration can I achieve? This is always the first customer’s question and frankly there is no straight answer because the result depends on the complexity of both the design and the testbench. Usually a good estimation can be obtained from running simulation profiling and then applying Amdahl’s rule. However, the best way to verify acceleration potential is just to experiment with a typical design, so we have created a simple design of a memory sub-system using Xilinx Vivado Design environment. It contains MIG controller for DDR3, AXI interconnect, two AXI traffic generators and one AXI protocol checker as shown in the following diagram.
Figure 3: Diagram created for memory subsystem benchmarking
Benchmark Results
Workstation and software used for benchmarking:
Workstation:
CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz
RAM: 32 GB
HES Board: HES7XV4000BP_REV2, contains 2x Virtex7 2000 FPGA
Software:
OS: Linux CentOS 6, x86_64
Simulator: Riviera-PRO 2017.02
Design env: Vivado 2016.4
Acceleration env: HES-DVM 2017.02
If you are interested in further details about this project, benchmark, and tools which can significantly accelerate your simulation you can view the following application note: https://www.aldec.com/en/support/resources/documentation/articles/1915
Tags: acceleration, co-simulation, FPGA, HES-DVM, simulation, SoC and ASIC Prototyping, verification, Xilinx
No Comments »
Thursday, June 1st, 2017
 The SoC domination observed so far in the ASIC industry is coming to the FPGA world and changing the way FPGAs are used and FPGA projects are verified. The latest SoC FPGA devices offer a very interesting alternative of reprogrammable logic powered with the microprocessor, usually ARM. With new types of devices there is always a need for extended verification methodology. SoC ASIC has so far been the main pioneer for advanced and highly scalable verification methodologies. Due to the complexity and size of such projects, ASIC labs were actually driving EDA vendors to deliver verification solutions for their projects.
With the growth of these projects, hardware emulation became a common tool which was then integrated with virtual platforms and labeled ‘hybrid co-emulation’. This hybrid solution offered a single verification platform for both software and hardware teams. Such platforms allow the performance of verification at the SoC level, allowing the entire project to be verified before the final design code is actually written and available for example, to perform the prototyping.
Hybrid emulation allows the connection of the work environment of software teams using virtual platforms with the hardware engineers using emulators. Why is this so important? The issue is, until now the software portion of the project worked on the virtual models, separate from the hardware portion. Connecting these two domains allows for testing of the project at the SoC level instead of the subsystems level, which in turn increases the coverage of testing and enables the detection of problems much earlier.
Figure 1 – Hybrid co-emulation verification system.
(more…)
Tags: Active-HDL, ARM, asic, FPGA, FPGAs embedded processors, Hardware Emulation, Hardware-Assisted Verification, high level synthesis, RTL simulator kernel efficiency, SoC and ASIC Prototyping, soc design verification, verification
No Comments »
Tuesday, May 31st, 2016
 When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A database works much the same way, a collection of information that is stored and accessed on demand.
Take the UVM configuration database for example. It basically acts as a repository so that when the time comes, certain portions of the UVM testbench can be obtained from the database and used to build the structure.
When items are placed in the database with a set() method (uvm_config_db::set()), components in lower levels will call the get() method in order to obtain the necessary parts to build the verification framework.
Sharing an interface
If I were to ‘set’ an interface from my top level into the database while simultaneously giving it an identifying name, officially referred to as the ‘field name’, I could later use the field name to retrieve that interface in my driver to connect to the DUT by calling the get() method (uvm_config_db::get()).
Fig. 1) Setting the interface in the configuration database using an identifier ‘my_identifier’
Fig. 2) In order to connect a monitor or driver to the dut, the get() function will need to be called to access the interface in the respective build phase.
Setting up configurations
 If I wanted to change or modify my testbench structure, I could create a ‘configuration’. In my configuration, I could specify some rules as to what components I want my testbench to have. If I am designing a processor where I’ve already loaded up the memory with instructions, there’s no need to generate stimulus, therefore I could eliminate the driver and sequencer.
This is what UVM refers to as passive and active modes. Passive mode is where only a monitor exists to observe data and active mode is where a driver and sequencer are needed to generate stimulus. Placing certain variables in the configuration database can help to determine whether the testbench is setup as passive or active.
In order to declare the testbench as passive or active, a configuration object is created. The built in uvm_active_passive_enum data type is used to indicate whether the testbench is UVM_ACTIVE or UVM_PASSIVE.
Fig. 3) An example configuration
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Riviera-PRO, simulation, uvm, verification
1 Comment »
Tuesday, May 31st, 2016
 I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That’s the conventional wisdom, and most of the time it holds up.
But there’s one area where this Texas city feels right at home in the rest of the Lone Star State, and that’s the cuisine. Go into the almost any trendy restaurant, and it’s possible to order a meal that has bacon in everything. Whether it’s the Paleo influence, or the craft food movement, or a remnant of good old Southern cooking, there are a lot of meaty options.
That’s great, you say, except I don’t care how ethically sourced the pork is. Dude, I’m a vegetarian.
Never fear. If you plan to visit our fair city for our industry’s upcoming Design Automation Conference (DAC 2016), rest assured you can find great vegetarian dining options in and around downtown Austin. And while UBER may have left Austin, you can still walk or catch a cab from your hotel or the Convention Center to visit these great restaurants (scroll down for map).
Mainstream Options: You’re a Vegetarian, But the Rest of Your Party Wants Meat
A. The Flagship Whole Foods, one mile west of downtown Austin, is a great place for a working lunch. I know, you’re thinking, You want me to eat at a grocery store? This is not just any grocery store, my friend. It is a food bazaar that will absolutely blow you away. Rows of tempting salad bars allow you to compose your own meal, but there are also vegan and vegetarian options at just about every food counter and a pleasant roof-top terrace where you can enjoy your food. Whole Foods Market. 525 North Lamar, Austin, Texas. 512.542.2200. $
B. 24 Diner, like many Austin restaurants, was featured on the Food Network, with the result that this trendy spot can be mobbed. Its allure is comforting food served all night long, with plenty of vegetarian options, like veggie hash, mushroom and veggie burgers, and a variety of tempting salads. 24 Diner. 600 Lamar. 512.472.5400. $$
C. I love the intimacy of Koriente, a Korean health food restaurant with garden dining tucked into a little warren of shops and restaurants at the east end of Sixth Street, right before you hit the I 35 overpass. It was founded by a mom who hated to cook and wanted to make a place where other moms could bring their families for nourishing, healthy, delicious food. Most of the entrees are vegetable based; for a couple extra bucks, add meat and eggs to the mix. But you might want to walk over from your hotel. Parking is at a minimum here. Koriente. 621 East 7th. 512.275.0852. $
D. The Blue Dahlia Bistro is right across the highway in the heart of East Austin, still walking distance from downtown. The restaurant’s promise is that you can “relax and feel like you are in the European countryside.” That might be a tiny stretch, but I have to admit — they do have a truly cozy and inviting outdoor space. They serve yummy French-inspired dishes and have a good selection of vegetarian options, including an all-day breakfast menu. The Blue Dahlia.1115 East 11th Street. 512.542.9542. $
Hardcore and Retro: You Won’t Find Meat on Any of These Plates
E. If you’re looking for a glimpse of the Austin of Slackerfame, venture a few miles north to the University neighborhood of Hyde Park, where Mother’s Cafe has been dishing up family style vegetarian and vegan cuisine since 1980. The restaurant has spruced up with a recent makeover, but they haven’t really changed their menu. There’s nowhere else in town where you can order Mushroom Stroganoff or BBQ Tofu. Ask to be seated in the Garden Room, an Austin tradition. Mother’s Cafe. 4215 Duval. 512.451.3994. $
F. Casa de Luz, located about a half mile from downtown, in the hippest part of East Austin, describes itself as Austin’s “only all-organic dining and community center.” They take good nutrition very seriously here; even the drinking water that serve is filtered to remove fluoride. Each day, they prepare a different menu from scratch, using plant-based foods. That means most of the food they serve is vegan as well. Casa de Luz. 1701 Toomey Road. 512).476.2535. $
G. Mr. Natural lets you enjoy Tex-Mex cuisine without worrying that someone is sticking lard in those beans. The East Austin restaurant is 100 percent vegetarian, and the place also includes a juice bar and a bakery that has won several awards, including “Best Tres Leches” from the Austin Chronicle.That is really saying something: the recipe is vegan. Mr. Natural. 1901 Cesar Chavez. 512.477.5228. $
H. There aren’t a lot of 100 percent vegan options in the Weird City, but East Austin Counter Culturefits the bill. Whenever possible, the chefs here try to use ethically sourced and organic ingredients, and their menu is a combination of classic vegetarian dishes like Lentil Loaf and Mac and Cheeze (the “cheese” made from cashews) and curiosity-inspiring fare such as the Jackfruit BBQ Sandwich. They also serve gluten-free pizza. Counter Culture.2337 East Cesar Chavez. 512.524.1540.
Quick and Trendy Veggie Bites
I. You can’t talk about food in Austin without at least a nod to one of the city’s many food trucks. Arlo’s is the place to go downtown for a late night vegan burger or seiten “chicken” patty. You want fries with that? No problem. Arlo’s. 900 Red River. 512.840.1600. $
J. And for dessert? Lick Honest Ice Creams offers a variety of “weird” flavors — I love the roasted beet and fresh mint — including some vegan options. The staff lets folks sample as many flavors as they like, so the line might move slowly!, Suite 1135. 512.363.5622. $
Well there you have it. You see, if you’re a vegetarian or looking to have a meal with vegetarian colleague or client, Austin has you covered.
I hope you’ll find these tips useful. If you have any other questions about our fair city, please stop by and see me at DAC Booth #619. If you’d like to learn more about Aldec’s Scalable Emulation Solutions or ASIC Verification Spectrum, I hope you’ll register for a one-on-one presentation at DAC, or call +1-702-990-4400 or email us at sales@aldec.com.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: asic, Emulation, SoC and ASIC Prototyping, verification
1 Comment »
Monday, May 23rd, 2016
 The hardest part of DO-254 is not the requirements. It’s not the design. It’s not the verification.
We just wrapped up this year’s 3-day DO-254 Practitioner’s Course, and each year I learn something new. In this year’s training we had attendees from major aerospace companies including Curtiss Wright, Rolls Royce, Sierra Nevada Corporation, Thales and Woodward. It’s always a pleasure to meet the aerospace folks and learn about their projects, goals and challenges. This is the fifth year we’ve done these trainings and each time I pick up subtle points from the instructor showing his impressive expertise in the subject.
This year’s subtle point that I picked up is about the hardest part of DO-254.
The hardest part of DO-254 is the cultural change that needs to take place in order for the organization to successfully comply to DO-254. This can be the make or break of the project. It doesn’t matter if you have top-notch planning documents if no one will adhere to them. It doesn’t matter if you’ve written 1000+ page requirements document, but the verification engineers cannot use them because the requirements are not verifiable. It doesn’t matter if you have the best design standards if your designers would not abide by them. It doesn’t matter if you have the latest verification tools but no one in your team understands how to satisfy tool assessment and qualification. It doesn’t matter if you have the most comprehensive review checklists if your reviewers will not use them and document the review activities and results.
DO-254 is a collection of industry best practices and all of its processes are tightly integrated, but it doesn’t matter if you have the DO-254 processes tightly in place if your team members will not abide by them. The hardest part of DO-254 is the cultural change that needs to be embraced by all team members. The cultural change is what can get you.
Many organizations new to DO-254 are eager to jump on board and start applying DO-254 to their projects due to its high demand in the avionics industry. You might be ready to take the leap and make the cultural change yourself, but is the rest of your team and organization ready for the cultural change?
If you’d like to learn more, or register for next year’s class, call us at 1+702-990-4400 or email training@aldec.com.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: do-254, FPGA, safety-critical, SoC and ASIC Prototyping, Traceability, verification
No Comments »
Tuesday, May 10th, 2016
 Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.
Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.
A Basic ASIC Verification Flow
Managing verification for ASICs requires a well-defined verification plan. Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.
While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
(more…)
Tags: acceleration, asic, Emulation, linting, prototyping, simulation, SoC and ASIC Prototyping, verification
No Comments »
Wednesday, April 6th, 2016
 I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full digital models to our doctors who can then poke, prod, and examine us remotely.
This is essentially what the UVM register layer allows and does. The UVM register layer acts similarly by modeling and abstracting registers of a design. It attempts to mirror the design registers by creating a model in the verification testbench. By applying stimulus to the register model, the actual design registers will exhibit the changes applied by the stimulus.
The benefit of this approach comes from the high level of abstraction provided. The bus protocols for accessing registers can change from design to design, but any stimulus developed for verification of the registers doesn’t have to. This makes it easy to port code from one project to the next if the registers are the same. Taking a look at Fig. 1 provides a better understanding of what a register model implementation might look like with respect to the UVM environment.
(more…)
Tags: simulation, uvm, verification, verilog
No Comments »
Wednesday, April 6th, 2016
Doulos CTO, John Aynsley, and I will be presenting a free 1 hour training webinar, Acceleration-Ready UVM, on Wednesday April 13th, 2016. Learn more in this guest blog by John Aynsley, excerpted from the Aldec Design and Verification Blog.
Acceleration-Ready UVM
by Doulos CTO, John Aynsley
We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed?
Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.
(more…)
Tags: acceleration, Emulation, hardware, systemverilog, uvm, verification
No Comments »
Wednesday, February 10th, 2016
 One of the reasons I like using UVM is its tendency toward an organized structure and uniformity. Some may find it annoying to adhere to such a strict format in UVM, but I think it’s a good way to keep the basics of UVM engrained in your brain. You always want a good foundation and development of strong fundamentals in any endeavor. Verification is no different and UVM hammers the fundamentals home.
UVM has a great structure and organization paradigm. I consider there to be two distinct and fundamental elements in the UVM structure: Components and Objects. Now this characterization isn’t strictly correct because uvm_components are extended from uvm_objects, but I think they are used in such a way that warrants the distinction. I consider it similar to the idea of trucks and cars. In my view, trucks are also cars, but it’s useful to note the difference.
(more…)
Tags: debugging, resources, systemverilog, training, uvm, verification
No Comments »
Friday, January 22nd, 2016
 I like FPGAs. My first experience with an FPGA was my university final year project where I demonstrated BIST with four Xilinx© 3000 devices; this was before FPGAs had JTAG built in. Filling up these devices with ViewDraw schematics required many hours in front of a terminal. Fast track to today’s advances such as Xilinx UltraScale and Vivado HLx, and I hope you would agree things have moved on quite a bit.
Amid all this changes, however, there are some things that have remained constant. Those are the three things that are great about FPGAs: they are reprogrammable, reprogrammable, and, they are reprogrammable!
So how is this capability utilized? Here are three examples:
Electronic products using FPGAs:
I think it is important not look at FPGAs as some poor cousin of an ASIC. This view is from the days of LSI Logic and Xilinx marketing battles, when FPGAs were used for mopping up “glue logic”. Today an FPGA provides a massively parallel programmable digital platform with a lot of silicon IP, such as high-performance interfaces. This capability is widely used by many industries now; it is not solely driven by the volume of parts. Today, you even find FPGAs in consumer products.
(more…)
Tags: acceleration, asic, embedded, FPGA, hardware, project management, university, verification, Xilinx
No Comments »
|
FPGA Design Verification Challenge
