Posts Tagged ‘Emulation’
Tuesday, August 11th, 2020
 In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible.
Designs that are described at a higher level of abstraction are less prone to human errors. High-level descriptions of designs are done without significant concern regarding design constraints. The conversion from high-level descriptions to gates is done by using synthesis tools. These tools use various algorithms to optimize the design as a whole. This circumvents the problem with different designer styles for the different blocks in the design and sub-optimal design practices. Logic synthesis tools also allows for technology independent designs. Logic synthesis technology was commercialized around 2004, and since then it’s been part of the standard EDA tool chain for ASICs and FPGAs.
(more…)
Tags: acceleration, Active-HDL, design, embedded, Emulation, FPGA, FPGA Simulation, HDL, HES-DVM, Intel, Synthesis, systemverilog, verilog, Xilinx
No Comments »
Monday, May 4th, 2020
 These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it.
Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and software testing. Thus, IC design emulation is an increasingly popular technique of verification with hardware-in-the-loop.
Recently, hardware assisted verification became much more affordable thanks to the availability of high capacity FPGAs (like Xilinx Virtex UltraScale US440) and their adoption for emulation by EDA vendors.
A good example of such an emulation platform is Aldec’s HES-DVM. It can accommodate designs over 300 Million ASIC gates on multi-FPGA boards (HES-US-1320), where the capacity scales by interconnecting multiple boards in a backplane.
(more…)
Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, simulation, SoC, verification
No Comments »
Wednesday, February 19th, 2020
Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge.
Early access to hardware-software co-verification allows hardware and software teams to work concurrently and set the foundation to a successful SoC project. However, many co-emulation methodologies are based on processor virtual models which are not accurate representations of the design. Fortunately, Aldec has a solution that integrates an ARM-based SoC from Xilinx, specifically a Zynq UltraScale+ MPSoC, with the largest Xilinx UltraScale FPGA. Since the Zynq device includes the hard IP of the ARM processor, our solution provides an accurate representation of the ARM-based SoC design for co-verification.
(more…)
Tags: ARM, asic, embedded, Emulation, FPGA, HES-DVM, SoC, SoC and ASIC Prototyping, Validation, verification, Zynq
No Comments »
Thursday, January 25th, 2018
 A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory reduces data hiccups and minimizes message loading and buffering times. But is that enough?
Because of the huge amount of data that people now generate – combined with the wealth of communication protocols, such as Wi-Fi, Ethernet, USB, SFP, QSFP – high-performance, hardware re-programmable routers are becoming popular. That hardware re-programmability is being delivered through FPGAs, and utilizing one as the main ‘processor’ on the router makes it easy to add or modify desired modules such as encryption and compression.
(more…)
Tags: acceleration, design, digital, embedded, Emulation, FPGA, hardware, industrial, prototyping, SoC, SoC and ASIC Prototyping, Xilinx
No Comments »
Wednesday, November 22nd, 2017
 For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA based emulation became available – and I’m not talking here about FPGA prototyping.
“Emulation – Prototyping, aren’t they just synonyms?”
Sure, they are not. The most significant differences between FPGA usage in prototypes and in emulation are shown in table 1.
|
|
Prototyping
|
Emulation
|
|
Clock frequency
|
10-200 MHz
|
1-20 MHz
|
|
Clock Topology
|
Multiple asynchronous sources – limited number of domains
|
Derived from emulation core clock – unlimited number of domains
|
|
Speed Limitation
|
Fixed,
Determined by Inter-FPGA signal multiplexing
|
Adaptive,
Determined by FPGA-to-Host Comms, Inter-FPGA signal multiplexing
|
|
Stimulus Source
|
In-System, Real-world IO
|
Host,
Connection with simulators, virtual platforms, virtual models and other testbenches
|
|
Signal Capture
|
Selected Nodes
|
Full Visibility
|
|
Memory Models
|
Near-match to physical
|
Modelled
|
|
Design Setup
|
Computer aided but with extensive user’s input and decisions
|
Fully automated
|
Table 1: Typical differences between FPGA usage in prototyping and emulation
FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz.
“FPGAs are way too small for our SoC design, aren’t they?”
In the HES-US-2640 board, Aldec already has the largest capacity single FPGA boards commercially available today. Connecting 4 such boards in a backplane gives you 24 largest Xilinx UltraScale chips in which you can implement 633 Million ASIC Gates and still have 40% of capacity margin to facilitate FPGA Place & Route.
Figure 1: Scalable HES platform for prototyping & emulation
Not all designs need such excessive capacity, especially IoT projects, where the primary requirement is small footprint and energy-safe design. You will find the proper configuration in Aldec HES boards versatile portfolio containing Virtex-7, Virtex UltraScale and Kintex UltraScale based hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Emulation, FPGA, hes-boards, prototyping
No Comments »
Thursday, June 15th, 2017
‘The cloud’ has been an industry buzz word for some time now and whilst the initial focus was on data storage and sharing – and spawned the likes of Dropbox – ‘cloud computing’ is currently the latest trend. For instance, Amazon’s cloud platform, Amazon Web Services (AWS), gives users access to servers and a range of applications. Storage is available as before but so too now are dedicated relational databases; which in Amazon’s case is provides through a different service.
Enterprise businesses are taking advantage of cloud computing platforms, and for a number reasons. These include pay-as-go (as opposed to investing considerable cap ex), speed and flexibility (resources and storage can be made available quickly), and one is spared the headache of maintaining a mass of IT hardware and keeping on top of software license renewals.
Also, earlier this year Amazon announced EC2 (Elastic Compute Cloud) F1, a compute instance with FPGAs that users can program to perform hardware accelerations. The F1 instance includes an FPGA developer Amazon Machine Image (AMI) which includes a development environment with scripts and tools for code compilation and design simulation.
It is expected the primary users of EC2 F1 will be software developers, working on complex and compute-intensive algorithms for which FPGAs lend themselves particularly well. For instance, High Performance Computing will increasingly exploit FPGA technology.
But let’s not forget one of the most important roles that FPGAs have been playing in our industry – EDA – for a number of decades: hardware acceleration for ASIC prototyping purposes.
(more…)
Tags: Active-HDL, Emulation, FPGA-based hardware emulation platform, hardware, Hardware Emulation, HES-DVM, mixed language simulations, SoC and ASIC Prototyping, system c, system verilog, utilise Virtex-7, verilog, VHDL, Virtex UltraScale FPGAs, Virtex-7
No Comments »
Tuesday, May 31st, 2016
 I moved to Austin a little over a year ago, and have quickly learned that this city is a progressive blue island in a sea of red. That’s the conventional wisdom, and most of the time it holds up.
But there’s one area where this Texas city feels right at home in the rest of the Lone Star State, and that’s the cuisine. Go into the almost any trendy restaurant, and it’s possible to order a meal that has bacon in everything. Whether it’s the Paleo influence, or the craft food movement, or a remnant of good old Southern cooking, there are a lot of meaty options.
That’s great, you say, except I don’t care how ethically sourced the pork is. Dude, I’m a vegetarian.
Never fear. If you plan to visit our fair city for our industry’s upcoming Design Automation Conference (DAC 2016), rest assured you can find great vegetarian dining options in and around downtown Austin. And while UBER may have left Austin, you can still walk or catch a cab from your hotel or the Convention Center to visit these great restaurants (scroll down for map).
Mainstream Options: You’re a Vegetarian, But the Rest of Your Party Wants Meat
 A. The Flagship Whole Foods, one mile west of downtown Austin, is a great place for a working lunch. I know, you’re thinking, You want me to eat at a grocery store? This is not just any grocery store, my friend. It is a food bazaar that will absolutely blow you away. Rows of tempting salad bars allow you to compose your own meal, but there are also vegan and vegetarian options at just about every food counter and a pleasant roof-top terrace where you can enjoy your food. Whole Foods Market. 525 North Lamar, Austin, Texas. 512.542.2200. $
B. 24 Diner, like many Austin restaurants, was featured on the Food Network, with the result that this trendy spot can be mobbed. Its allure is comforting food served all night long, with plenty of vegetarian options, like veggie hash, mushroom and veggie burgers, and a variety of tempting salads. 24 Diner. 600 Lamar. 512.472.5400. $$
C. I love the intimacy of Koriente, a Korean health food restaurant with garden dining tucked into a little warren of shops and restaurants at the east end of Sixth Street, right before you hit the I 35 overpass. It was founded by a mom who hated to cook and wanted to make a place where other moms could bring their families for nourishing, healthy, delicious food. Most of the entrees are vegetable based; for a couple extra bucks, add meat and eggs to the mix. But you might want to walk over from your hotel. Parking is at a minimum here. Koriente. 621 East 7th. 512.275.0852. $
D. The Blue Dahlia Bistro is right across the highway in the heart of East Austin, still walking distance from downtown. The restaurant’s promise is that you can “relax and feel like you are in the European countryside.” That might be a tiny stretch, but I have to admit — they do have a truly cozy and inviting outdoor space. They serve yummy French-inspired dishes and have a good selection of vegetarian options, including an all-day breakfast menu. The Blue Dahlia.1115 East 11th Street. 512.542.9542. $
Hardcore and Retro: You Won’t Find Meat on Any of These Plates
E. If you’re looking for a glimpse of the Austin of Slackerfame, venture a few miles north to the University neighborhood of Hyde Park, where Mother’s Cafe has been dishing up family style vegetarian and vegan cuisine since 1980. The restaurant has spruced up with a recent makeover, but they haven’t really changed their menu. There’s nowhere else in town where you can order Mushroom Stroganoff or BBQ Tofu. Ask to be seated in the Garden Room, an Austin tradition. Mother’s Cafe. 4215 Duval. 512.451.3994. $
F. Casa de Luz, located about a half mile from downtown, in the hippest part of East Austin, describes itself as Austin’s “only all-organic dining and community center.” They take good nutrition very seriously here; even the drinking water that serve is filtered to remove fluoride. Each day, they prepare a different menu from scratch, using plant-based foods. That means most of the food they serve is vegan as well. Casa de Luz. 1701 Toomey Road. 512).476.2535. $
G. Mr. Natural lets you enjoy Tex-Mex cuisine without worrying that someone is sticking lard in those beans. The East Austin restaurant is 100 percent vegetarian, and the place also includes a juice bar and a bakery that has won several awards, including “Best Tres Leches” from the Austin Chronicle.That is really saying something: the recipe is vegan. Mr. Natural. 1901 Cesar Chavez. 512.477.5228. $
H. There aren’t a lot of 100 percent vegan options in the Weird City, but East Austin Counter Culturefits the bill. Whenever possible, the chefs here try to use ethically sourced and organic ingredients, and their menu is a combination of classic vegetarian dishes like Lentil Loaf and Mac and Cheeze (the “cheese” made from cashews) and curiosity-inspiring fare such as the Jackfruit BBQ Sandwich. They also serve gluten-free pizza. Counter Culture.2337 East Cesar Chavez. 512.524.1540.
Quick and Trendy Veggie Bites
I. You can’t talk about food in Austin without at least a nod to one of the city’s many food trucks. Arlo’s is the place to go downtown for a late night vegan burger or seiten “chicken” patty. You want fries with that? No problem. Arlo’s. 900 Red River. 512.840.1600. $
J. And for dessert? Lick Honest Ice Creams offers a variety of “weird” flavors — I love the roasted beet and fresh mint — including some vegan options. The staff lets folks sample as many flavors as they like, so the line might move slowly!, Suite 1135. 512.363.5622. $
Well there you have it. You see, if you’re a vegetarian or looking to have a meal with vegetarian colleague or client, Austin has you covered.
I hope you’ll find these tips useful. If you have any other questions about our fair city, please stop by and see me at DAC Booth #619. If you’d like to learn more about Aldec’s Scalable Emulation Solutions or ASIC Verification Spectrum, I hope you’ll register for a one-on-one presentation at DAC, or call +1-702-990-4400 or email us at sales@aldec.com.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: asic, Emulation, SoC and ASIC Prototyping, verification
1 Comment »
Monday, May 23rd, 2016
 Recently I read a Semiwiki article, Army of Engineers on Site Only Masks Weakness, in which author Jean-Marie Brunet of Mentor Graphics wrote that FPGA Prototyping requires an army of tech support engineers on-site to mask the weaknesses of FPGA prototyping flows. As the Tech Support Manager for Aldec Hardware Emulation Solutions, I have to admit I’ve never had to deploy an army onsite.
It is true that FPGA Prototyping is more challenging than emulation. Yet, for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation.
(more…)
Tags: Emulation, FPGA, prototyping, SoC and ASIC Prototyping, Xilinx
No Comments »
Tuesday, May 10th, 2016
 Aldec has, over the last 30 years, established itself as the preferred provider of high-performance, cost-effective verification tools for use in proving out complex FPGA designs. As the logic capacity and capability of FPGAs have increased, however, the distinction between FPGA and ASIC design has narrowed. A modern FPGA verification flow looks very much like an ASIC verification flow.
Small and large fabless companies alike need a reliable verification partner that suits their budgets while still providing a high level of support. To answer the call, we at Aldec have extended our spectrum of verification tools for use in digital ASIC designs.
A Basic ASIC Verification Flow
Managing verification for ASICs requires a well-defined verification plan. Efficient verification planning starts with functional and design requirements in which requirements are mapped to verification methods, scenarios, goals and metrics, coverage groups, and results. Mapping entails traceability throughout the project that must be well maintained so that changes in the requirements will seamlessly reflect potential changes downstream to the elements of the verification plan.
While traceability can benefit any design, it is mandatory for safety-critical designs regulated by standards such as ISO-26262 for automotive, IEC-61508 for industrial and DO-254 for avionics.
(more…)
Tags: acceleration, asic, Emulation, linting, prototyping, simulation, SoC and ASIC Prototyping, verification
No Comments »
Wednesday, April 6th, 2016
Doulos CTO, John Aynsley, and I will be presenting a free 1 hour training webinar, Acceleration-Ready UVM, on Wednesday April 13th, 2016. Learn more in this guest blog by John Aynsley, excerpted from the Aldec Design and Verification Blog.
Acceleration-Ready UVM
by Doulos CTO, John Aynsley
We hear that emulation is one of the fastest-growing segments in EDA right now, yet simulation still continues to be the main workhorse for functional verification, and SystemVerilog and UVM are everywhere you look. But how do you combine the two? How do you run a UVM-based constrained random verification environment alongside an emulator and get reasonable execution speed?
Many vendors have solutions, including Aldec with their HES-DVM™ emulator. Their solution is based on the Accellera SCE-MI standard, and in particular on SV-Connect, which is a function-based interface that uses the SystemVerilog DPI (Direct Programming Interface) to pass information between the host and the emulator. You partition your UVM drivers and monitors into two parts, a small proxy that remains on the host and a synthesizable implementation that goes into the emulator. That way, all of the low-level timing detail is removed from the UVM code running on the host and is placed in the emulator, where it belongs. The communication between the host and the emulator can be optimized to avoid the emulator being stalled while waiting for the slower UVM simulation running on the host.
(more…)
Tags: acceleration, Emulation, hardware, systemverilog, uvm, verification
No Comments »
|
In the early days of digital design, all circuits were designed manually. You would draw K-map, optimize the logic and draw the schematics. If you remember, we all did many logic optimization exercises back in college. It was time consuming and very error prone. This works fine for designs with a few hundred gates, but as the designs get larger and larger this became non-feasible.
