Posts Tagged ‘design’
Wednesday, April 9th, 2014
 Imagine if you could look into the future…
– See the impact of requirements changes before they occur.
– Know with certainty which lines of code in an HDL design or testbench file needed to be re-evaluated based on a change request.
– Understand how a requirement change impacts the project schedule to help plan and allocate resources effectively.
Impact Analysis Defined
Seeing the future is possible with Impact Analysis, a practice within the change control process of product development. Impact Analysis provides information on what design and verification elements, artifacts, hardware components and materials, personnel, assets or activities that may be affected due to a requirement change. Armed with Impact Analysis data, you can then determine which elements to re-evaluate, modify, and even re-create if necessary.
(more…)
Tags: Aldec, conceptual design, design, do-254, FPGA, FPGA Design, fpga requirements, HDL Design, ibm doors, Impact Analysis, impact analysis defined, log files, post-layout design, requirements-based test cases, simulation runs, spec-tracer requirements lifecycle management solution, Testbench, Traceability, verification, waveforms
No Comments »
Friday, January 10th, 2014
 When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
(more…)
Tags: aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
No Comments »
Monday, September 9th, 2013
 You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.
Let’s break down just one part of the “How” or implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, clocks, design, hand-coded rtl, hardware design flow, hierarchies, high level synthesis, hls tool, processes, rtl, SoC, SoC and ASIC Prototyping, systemc, technology, Validation, verification
No Comments »
Wednesday, August 28th, 2013
 As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.
The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.
(more…)
Tags: Aldec, assertions, cen, chinese electronics news, co-simulation, coverage, debugging, debugging tools, design, digital, documentation, FPGA, fpga design simulation solution, fpga designs, HDL, ieee, matlab, os-vvm, project management, semiconductor industry, simulation, simulation platform, standards, top fpga design, university, verification, verification platform, verilog, VHDL, Xilinx
No Comments »
Thursday, August 22nd, 2013
Dr. Benjamin Carrion Schafer, Assistant Professor at Hong Kong Polytechnic University (and longtime fan of Aldec’s latest offering, CyberworkBench from NEC) was kind enough to author a guest blog for Aldec. Here’s an excerpt:
My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth – was that they had hired a magician.
This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.
As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, ansi-c, c/systemc code, dac, design, distributorship, hls, ide, nec cyberworkbench, qor visualization tool, rtl simulation, SoC, SoC and ASIC Prototyping, systemc, Validation, verification, verification process
No Comments »
Monday, August 12th, 2013
Fast Track to SystemVerilog for Verilog Users
The ability to adopt methodologies and get up to speed quickly is critical in today’s fast moving environment. Aldec offers Fast Track™ ONLINE trainings designed for busy engineers to increase their productivity and enhance their skill level from the comfort of their own browser.
Got SystemVerilog? While it may be a fashionable topic among verification engineers, it’s generally a shunned subject among hardware designers. While there are many good reasons for this (overgrown size of the SystemVerilog standard, expensive options required to use many language features in simulation, poor support in low-end tools, etc.), designers familiar with classical Verilog can benefit greatly from the features available in the Design Subset of SystemVerilog. Designing state machines is one excellent example. It is as easy and elegant in SystemVerilog as it is in VHDL – and those machines even synthesize in better tools!
(more…)
Tags: Aldec, design, design subset of systemverilog, fast track online trainings, simulation, system verilog, training, verification, verilog, VHDL
No Comments »
Tuesday, July 30th, 2013
 Retargeting Legacy Designs for New Technology
Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs.
I recently encountered a customer with a legacy design developed in block diagram format. If he hadn’t been an Aldec customer, he might have been stuck. Fortunately, Aldec Active-HDL™ provides utilities for importing legacy schematic based designs from Xilinx® Foundation Series, ViewLogic™, ViewDraw™, Active-CAD™ or any schematic tools that can output an EDIF netlist.
(more…)
Tags: active-cad, active-cad format, Aldec, design, eda tools, edif netlist, importing legacy schematic based designs, schematic tools, verilog, VHDL, viewdraw, viewlogic, Xilinx, xilinx foundation series, xilinx virtex
No Comments »
Monday, July 22nd, 2013
 To Accelerate DSP Design Development
If we’re being honest, human beings, especially engineers, are lazy. Let’s face it, most inventions ever made were created for the sole purpose of making our lives easier. The same goes for the manner in which we create our designs. In the not so distant past, engineers were drawing designs by hand on huge trace paper, placing them one below the other to form layers. This sounds like hard work to me! The lazy me would have wanted a smart (read: easy) solution to this process. Then along comes the EDA industry, which Aldec has been part of since 1984, making it much easier for us to do our designs.
Some might argue that EDA was born out not out of laziness, but in fact neccessity, due to increasing design complexity. True, it is impossible to imagine how the pencil and paper method could even work today. The point is it didn’t, and we now have automated the process to such an extent all you need do is enter some parameters in a tool wizard.
(more…)
Tags: accelerate dsp design development, Aldec, co-simulation, data analysis, data visualization, debugging, design, dsp algorithm, eda industry, edif cells, hdl code, hdl simulator, matlab, simulink, verification, verilog modules, vhdl entities
No Comments »
Thursday, May 16th, 2013
 This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.
We invite you to register at www.aldec.com/dac2013 to attend a technical sessions led by Aldec’s top engineers from all over the world. I can’t stress enough how important it is to pre-register since these sessions do fill up quickly. You’ll also get a free t-shirt when you attend one of our sessions – we’ve designed some pretty cool ones to give away this year.
Aldec has also teamed up with Agilent to deliver a DAC Insight Presentation on Wireless Algorithm Validation Wednesday, June 5, 2013 from 2:00-4:00pm. Learn more.
(more…)
Tags: acceleration, asic, design, DO-254 Compliance, Emulation, FPGA, FPGA Design, Functional Verification, HES, HES-7, require life cycle management, SoC, SoC and ASIC Prototyping, specialized application
No Comments »
|
Imagine if you could look into the future…
