Archive for the ‘Specialized Applications’ Category
Thursday, December 11th, 2014
Well folks, last call from Engineer Santa. Aldec’s #12DaysofUsefulGifts giveaway will end this Friday, December 12 at 12pm midnight Pacific Standard Time.[preview_cut]
If you haven’t registered yet, you’ll want to hurry and visit www.aldec.com/survey. There you will take a brief verification survey and be entered to win.
If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. If you are looking for some practical and useful gift ideas for the holidays, you might want to take a closer look. I’ve already talked about some of these from Days #1-4. We’ve given away more prizes since then and sent them to engineers all over the globe! Here, take a look…
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Tags: 1 Voice Beanie with Built-in Bluetooth Headphones, Aldec #12DaysofUsefulGifts giveaway, Anker Dual-Port Solar Charger, Anker Ultra Compact External Battery Charger, Etekcity Digital Laser Infrared Thermometer, Nike Air Jordan Hood Backpack Bag, SoC and ASIC Prototyping, XBOOM Ceramic Mini Portable Capsule Speaker
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Thursday, December 4th, 2014
Happy Holidays! We’ve made it to Day 4 of Aldec’s #12DaysofUsefulGifts giveaway. If you’ve been keeping up with us on Twitter and YouTube, you know that we’ve given away some fun prizes already. But that’s just the beginning, the prizes will get larger each day until the contest ends on December 12th!
If you are looking for some practical and useful gift ideas for the holidays, take a look at some of the fun prizes we’ve already given away.
To enter Aldec’s #12DaysOfUsefulGifts drawing, visit www.aldec.com/survey. There you will take a brief verification survey and automatically be entered to win. You only need to take the survey once to be eligible for daily drawings from Dec 1st-12th. You can also earn additional chances to win by sharing the contest link and viewing the daily contest video. Follow Aldec on Twitter where we will announce each day’s winner and unveil the next day’s prize. Good luck!
Tags: air vent mount for cell phones, Aldec #12DaysofUsefulGifts giveaway, aldec winning prizes, bushnell falcon 7x35 binoculars with case, grillight led bbq spatula, magisso tea cup, miles kimball manual hand held shredder, pocketmonkey wallet multi-tool, professional cleaning set for dslr cameras, SoC and ASIC Prototyping, sugru hardware sealer
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Tuesday, June 24th, 2014
 If you attended the Monday Night Reception at DAC 2014, you were greeted with a blast of 80s pop music. If you then said to yourself, “I’d like to meet the genius behind that idea” – that would be me. A few weeks before DAC, our marketing manager came to me with the task of being the DJ for the Monday night reception. As soon as I heard “DJ” I envisioned turntables, cool headphones, disco lights and all the fame that follows. My dreams were dashed a few moments later when she explained that I would only have a PA and a laptop.
Undaunted, I resolved to be the best DJ in the history of DAC Monday Night Networking Receptions. The first challenge was finding music everyone would enjoy. I naturally settled on 80s pop as my genre. I had the brilliant idea of picking a few songs from each year and playing it as a progressive 80s timeline during the evening. I changed my mind when I realized that bright idea would require some serious manual research and work.
Did I give up? Of course not. I did what any good engineer would do – I found an easy (and smart) solution that did not require substantial extra effort – a bit like re-using verification ip’s instead of making them from scratch. This level of engineering genius is often mistakenly perceived as laziness, but I like to call it being smart. In fact I recently wrote a blog on the topic of working smart not hard.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, aldec 30th anniverssary, aldec 30th birthday party, dac 2014, dac chat, embedded, gopro hero3+ camera, Hardware Emulation, safety-critical, SoC and ASIC Prototyping, training, uvm, uvm methodologies, verification, vhdl verification using osvvm
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Friday, January 10th, 2014
 When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
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Tags: Active-HDL, aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
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Monday, November 25th, 2013
 COMRATE™, the co-simulation solution developed by Aldec and Agilent is a lot like “couples-therapy” that can help get your digital blocks talking to the rest of your model-based design.
To illustrate, let’s take a look at a very basic model-level design and think about it from design-under-test perspective (i.e., what are the challenges associated with verifying this DUT):
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: agilent, Aldec, co-simulation, co-simulation flow, co-simulation solution, comrate, debugging, digital blocks, hdl models, mixed-signal, model-based design, multirate design, Riviera-PRO, system-level environment, system-level simulation, systemvue, verification, verification of multirate systems with multiple digital blocks
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Monday, September 9th, 2013
 You look confused. Perhaps I owe you an explanation. Anyone familiar with hardware design flow knows that it starts with specification and ends with implementation. The specification in this flow is the “What” – it defines what needs to be designed. The process for implementation is the “How” – it defines how you are going to achieve it.
Let’s break down just one part of the “How” or implementation – the Design Process. For many years hand-coded RTL has been used as the de facto method for implementation and it is still being used as predominant method for designing cutting-edge hardware. But does it follow that it is the most efficient method? I would say probably not, especially given the ever-growing complexity of the hardware.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, clocks, design, hand-coded rtl, hardware design flow, hierarchies, high level synthesis, hls tool, processes, rtl, SoC, SoC and ASIC Prototyping, systemc, technology, Validation, verification
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Thursday, August 22nd, 2013
Dr. Benjamin Carrion Schafer, Assistant Professor at Hong Kong Polytechnic University (and longtime fan of Aldec’s latest offering, CyberworkBench from NEC) was kind enough to author a guest blog for Aldec. Here’s an excerpt:
My first encounter with NEC’s CyberWorkBench (CWB) was in 2003 while attending DAC. Like most people, I was surprised to see a big Japanese company offering EDA tools. NEC is definitely known more for its consumer products and telecommunication equipment. I have to admit, the main reason I stopped at their booth – was that they had hired a magician.
This magician told the audience he would teach us a trick and give us a set of magic cards if we stayed until the end of the presentation. I did and I received my set of magic cards (which I still keep). At the same time I also became a CWB user and even wound up working for NEC.
As an assistant Professor at the Hong Kong Polytechnic University, I currently teach advanced VLSI courses and use CWB. It has some amazing capabilities. Let’s start with the fact that it supports ANSI-C and SystemC. Although SystemC might be a step in the right direction to have a unique standardized IEEE language, supported by all main HLS tools, it is not very intuitive and takes some time to master (especially if the user does not have a C++ background). Here is where ANSI-C support becomes very handy. Most people do know ANSI-C and it is very straightforward to convert any ANSI-C SW description into synthesizable C code.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Aldec, ansi-c, c/systemc code, dac, design, distributorship, hls, ide, nec cyberworkbench, qor visualization tool, rtl simulation, SoC, SoC and ASIC Prototyping, systemc, Validation, verification, verification process
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Thursday, May 30th, 2013
Free DAC INSIGHT Presentation
 At the fast-approaching Design Automation Conference (DAC) 2013 in Austin, TX, Aldec will co-host an INSIGHT Session with Agilent Technologies on how to validate a digital signal processing algorithm for both floating and fixed point levels. As Riviera-PRO Product Manager, I will join Agilent Senior Product Marketing Engineer FAE, Sangkyo Shin, on Wednesday, June 5th at 2pm in presenting a combined Agilent/Aldec FPGA flow that can be used to quickly validate communications digital signal processing (DSP) algorithms and accelerate physical layer (PHY) performance measurements.
  Mr. Shin will review the system-level design challenges and how to solve them using the SystemVue™ software, which provides the capabilities needed to evaluate and design modern communication systems and related products. I will then take the auto-generated HDL code from a system-level concept down to HDL simulation in Aldec Riviera-PRO™ and FPGA implementation on Aldec HES-5™ hardware prototyping board. Attendees will gain valuable insight on the cross-domain approach to traditional FPGA design flow and learn how to validate FPGA design for leading edge wireless and radar system with a system-level simulation tool integrated into the traditional hardware design flow.
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Tags: accelerate physical layer phy performance measurements, agilent, Aldec, aldec hes 5 hardware prototyping board, dac, debugging, dsp algorithms, FPGA, fpga design flow, hardware design flow, hdl debugging tools, hdl simulation, Riviera-PRO, riviera-pro product manager, systemvu software, validate communications digital signal processing, validate design, wireless algorithm validation
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Thursday, May 16th, 2013
 This year’s Design Automation Conference (DAC) will be held in Austin, Texas. If we survive the 70% humidity, our team looks forward to meeting you at Booth #2225 from June 3-5. Aldec HQ is located in Nevada just outside of Las Vegas… so we’re accustomed to more of a dry heat.
We invite you to register at www.aldec.com/dac2013 to attend a technical sessions led by Aldec’s top engineers from all over the world. I can’t stress enough how important it is to pre-register since these sessions do fill up quickly. You’ll also get a free t-shirt when you attend one of our sessions – we’ve designed some pretty cool ones to give away this year.
Aldec has also teamed up with Agilent to deliver a DAC Insight Presentation on Wireless Algorithm Validation Wednesday, June 5, 2013 from 2:00-4:00pm. Learn more.
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Tags: acceleration, asic, design, DO-254 Compliance, Emulation, FPGA, FPGA Design, Functional Verification, HES, HES-7, require life cycle management, SoC, SoC and ASIC Prototyping, specialized application
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