Archive for the ‘FPGA Design Creation and Simulation’ Category
Tuesday, October 4th, 2016
The Internet of Things (IoT) has become the main topic in the technological world; it seems everybody is talking about it as the next wave in electronic systems. The scope of the IoT is so wide now, some have suggested changing the name to the Internet of Everything. We now expect all devices we use in our personal and professional lives to be connected, starting from the obvious ones in smartphones and computers, going through wearables, smart home and security devices, to industrial automation applications, and of course automotive electronics.
Creating devices for the IoT is a big challenge for engineering teams at the design and verification levels, but also at the application and data levels. As all those devices (already estimated to number in the billions, and growing) start generating their data, IoT gateways and infrastructure will need to experience a new revolution. Clouds and data farms will become a common medium not only for data storage and message exchange, but also for processing and analytics which will require much more specialized computing power.
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Tags: Active-HDL, fpga acceleration, FPGA Design, internet of things, programmable soc, SoC and ASIC Prototyping, tysom board, tysom gateway, xilinx zynq soc
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Wednesday, August 17th, 2016
Today’s article is authored by Zach Nelson, Aldec FAE Intern. Zach is a Field Application Engineer Intern with Aldec, working in tandem with his fellow interns to develop hardware specific applications. He is set to graduate with a B.S. in Electrical Engineering from University of Nevada, Las Vegas in 2017. His field interests include ASIC Design & Solid State Electronics.
It’s time for Universities to say goodbye to their outdated FPGA boards and introduce the Xilinx® Zynq™ chip. The Zynq chip is a device which combines an FPGA fabric with a processing unit. The Zynq chip is very similar to other FPGA devices, but it does have a few key advantages and features that can enhance your designs and increase its capabilities.
What can Zynq do?
The Zynq chip has applications in the design fields related to:
- FPGA
- Digital Design
- VHDL/Verilog
- Embedded Systems
- Robotics
- IoT
- Factory Automation
- Algorithm Implementations
- Signal Processing
- Video/Image Processing
FPGA
The Programmable-Logic can be used in isolation of the processor which allows it to be used like a general FPGA device which can help support the topics covered in any VHDL/Verilog class as well as Digital Design. It is much easier to facilitate growth and learning in a project-based curiculum when you have a device such as the Zynq to interface with.
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Tags: Active-HDL, Aldec, embedded, FPGA, Xilinx, Zynq
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Wednesday, January 21st, 2015
 Happy New Year!
January brought an unseasonably warm wave of weather to Las Vegas as International CES converged on the city this month.
The size and scope of this worldwide consumer electronics tradeshow continues to grow each year with new products and industries on the rise, now driven by a phenomenon called the “Internet of Things” (IoT).
Shawn Dubravac, Ph.D., Chief Economist and Director of Research for the Consumer Electronics Association (CEA) kicked off the event by presenting a summary of his new book, “Digital Destiny”.
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Tags: Active-HDL, Aldec, Digital Design Verification, FPGA hardware platform, HES-DVM, International CES, internet of things, millions of ASIC gates, Multiple HES-7 FPGA development boards, Riviera-PRO, SoC and ASIC Prototyping, Xilinx Virtex-7
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Friday, January 10th, 2014
 When I first launched Aldec in 1984, home computers hadn’t quite taken off and innovations such as the compact disk and those oversized, power draining cellphones were still struggling to obtain mass acceptance.
Fast forward 30 years, even those of us in the electronics industry have whiplash from the speed at which technology is advancing and delivering new products. Buyers are more eager to become early adopters of innovative new technology, and smarter, faster tools are required to keep pace.
As a long-time member of the Electronic Design Automation (EDA) community, Aldec has had a front row seat to the technology race and over the years we have celebrated many successes of our own. Here, our product managers reflect on some of our most memorable highlights from 2013.
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Tags: Active-HDL, aldec founder, alint, ceo, class hierarchy visualization, comprehensive fpga vendor support, debugging, debugging tools, design, documentation, dynamic object debugging, dynamic object visualization, eda, electronic design automation community, fasttrack online training, FPGA Design, global project management, hes sw, hes-7 soc/asic prototyping, IP and Training Partner community, linting, microsemi, powerful simulation performance, riviera-pro debugging tool suite, rtax/rtsx prototyping solutions, SoC and ASIC Prototyping, spec-tracer requirements lifecycle management, support for uvm, sw validation platform, uvm, uvm-based verification environments, verification, vhdl-2008 support, xilinx zynq
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Wednesday, December 11th, 2013
 Here at the Aldec corporate office, we have a sign that reminds us all of our mission in the field of Technology. It reads, ‘To deliver solutions that provide the highest productivity to value ratio; supporting our existing products while delivering innovation to current and new technologies’. We have similar statements to reaffirm our commitment in the areas of Research, Alliances, and Culture – we call it our “Aldec DNA”.
 Because we genuinely want to have a clear understanding of our user’s requirements and methodology preferences, we continually engage in surveys and interviews. The knowledge we gain better positions us to support our existing products and to deliver that support where it matters the most to our users. If you’ve ever had that frustrating experience where your favorite tool no longer supports your methodology of choice – then you understand why this is so important.
Our Commitment to the VHDL Community
When it comes to VHDL-2008, we have learned from our customers that many are happy using the methodology – and continue to successfully deliver cutting-edge technology with it. So, while we remain committed to delivering innovation to new technologies, our R&D teams also invest a great deal of development time to ensure that Aldec solutions continue to offer a high level of support for popular languages like VHDL.
For the rest of this article, visit the Aldec Design and Verification Blog.
Tags: Active-HDL, advanced verification platform, Aldec, aldec design rule checker, aldec dna, aldec simulators, alint, bitvis, do-254/ed-80 vhdl rule plug-ins, eda industry, embedded psl, FPGA Design, functional coverage, HDL, highest productivity to value ratio, ieee, ieee 1076-1993 Standard, ieee 1076-2002 vhdl standard, ieee 1076-2008 standard, ieee standard, ieee vhdl, intelligent testbench methodology, open source vhdl verification methodology, osvvm, psl embedded in vhdl, randomization, Riviera-PRO, simulation, source encryption, standards, starc vhdl, vector implementation of integer arithmetic, verification, VHDL, vhdl community, vhdl designs, vhdl testbench, vhpi interfacing to C/C++ code
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Wednesday, August 28th, 2013
 As the proud Product Manager of Aldec’s FPGA Design Simulation solution, I am excited (like it was my first Cranberries concert) to announce that Active-HDL™ is celebrating 16 years since its initial release in 1997. Active-HDL has not merely stood the test of time, it has dominated the FPGA market like a Hulk Hogan smackdown with powerful simulation performance and debugging tools.
The key to Active-HDL’s long-term success lies in Aldec’s customer-centric philosophy. Simply put, we really do listen closely to our users and invest heavily in our tools. For this reason, continued simulation performance optimizations from release to release enable users to benefit from Active-HDL’s faster simulation even as the size of FPGA designs continues to grow.
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Tags: Active-HDL, Aldec, assertions, cen, chinese electronics news, co-simulation, coverage, debugging, debugging tools, design, digital, documentation, FPGA, fpga design simulation solution, fpga designs, HDL, ieee, matlab, os-vvm, project management, semiconductor industry, simulation, simulation platform, standards, top fpga design, university, verification, verification platform, verilog, VHDL, Xilinx
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Tuesday, July 30th, 2013
 Retargeting Legacy Designs for New Technology
Digital design has come a long way since its inception from drawing schematic on paper, to CAD tools which can be used to draw schematics, and to today’s most popular (and efficient) process of describing designs through HDLs.
I recently encountered a customer with a legacy design developed in block diagram format. If he hadn’t been an Aldec customer, he might have been stuck. Fortunately, Aldec Active-HDL™ provides utilities for importing legacy schematic based designs from Xilinx® Foundation Series, ViewLogic™, ViewDraw™, Active-CAD™ or any schematic tools that can output an EDIF netlist.
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Tags: active-cad, active-cad format, Active-HDL, Aldec, design, eda tools, edif netlist, importing legacy schematic based designs, schematic tools, verilog, VHDL, viewdraw, viewlogic, Xilinx, xilinx foundation series, xilinx virtex
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Monday, June 24th, 2013
 Productivity Boosting Features
Yes I did, but with no intention to start a holy war on which HDL editor is best. When it comes to HDL editors, each engineer has their own choice and I am not attempting to hurt any madly, deeply felt sentiments. My goal is only to bring the awareness to those using the HDL editor built into Active-HDL™ and to help them use it more efficiently.
There are two main categories for HDL editors (1) general purpose text editors, and (2) integrated text editors. Both have their own pros and cons, and in the end it is for each engineer to decide which suits their needs.
The HDL editor built into Active-HDL falls under the second category of integrated text editors. It offers many basic features (syntax highlighting, templates, columns selection, code folding, auto-formatting) as well as semantic features (code navigation, on-the-fly error detector), and also offers seamless integration with the simulator and version control system. The HDL editor in Active-HDL can be used with VHDL, Verilog, SystemVerilog, SystemC, C/C++, PSL, OVA, Perl scripts and Tcl scripts.
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Tags: Active-HDL, auto-formatting, c/c++, code analysis, code browser, code folding, code navigation, code template, columns selection, creating hdl text modules, HDL, hdl editors, on-the-fly error detector, ova, perl scripts, psl, syntax highlighting, system verilog, systemc, Tcl scripts, templates, value probes, verilog, VHDL
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