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 Aldec Design and Verification
Vatsal Choksi
Vatsal Choksi
Vatsal provides technical support for Aldec’s software products such as Active-HDL and Riviera-PRO. He is proficient in FPGA/ASIC digital design and verification.As a technical support engineer, Vatsal has deep understanding of verification languages such VHDL, Verilog/SystemVerilog, SystemC and … More »

Understanding the inner workings of UVM – Part 3

 
March 26th, 2018 by Vatsal Choksi

In this blog, I am going to discuss different phases that UVM follows.

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals varies then synchronicity lacks and thus verification can not be achieved as expected. That is the main reason why UVM has different phases.

The whole environment of UVM is structured on phases. They are active right from the beginning of the simulation to the end of the simulation. The topic discussed here will help people who are new to UVM. To start with, most of the phases are call back methods. The methods are either function or task. They are all derived from the UVM_Component class, same as other test-bench components. If you remember the first blog, we went through how to write a class. We understood the OOP concepts such as inheritance and even used them by extending the base class. Now, creating objects of the class is also important in order to use it as and when required. It is known as build_phase. This step takes place first. Next, after we write different classes, it is important to connect them. For example, if I write different classes with different functionality, at the end I provide them all under one top class. In Verilog it was top level module. In system Verilog it was class Environment. Under that main class, you connect all your semi classes which is known as connect_phase. Next, comes the end_of_elaboration_phase. By the time this phase becomes active, everything is connected and simulation next moment on wards is ready to begin.
Read the rest of Understanding the inner workings of UVM – Part 3

Do I really need a commercial simulator?

 
March 26th, 2018 by Sunil Sahoo

As an Applications Engineer I visit lots of potential customers, or talk to them at trade shows, who are doing FPGA designs but don’t own a commercial simulator. I ask them why that is. Most of the time it is budgetary restrictions. They don’t have funds to buy additional tools. I understand their situation and point out to them that at Aldec we have a very cost-effective simulator. But that is not what I want to talk about in this blog. I want to talk about engineers who say: “I am happy with the simulator my FPGA vendor provided me”, or “My simulations only take 15-20 minutes to run, I don’t think I need a faster simulator”, or “We don’t run simulations”.

That last response haunts me the most. For instance, at a recent site visit I was told: “We just load the design on our FPGA and test it out”. I asked how long does a full test iteration (i.e. program FPGA -> test -> debug -> re-code -> re-program) takes. They said about an hour or two, depending on the bug. I then asked how much of that time spent just running synthesis and programming the board? They said about 30 minutes.

Next, I proceeded to explain the benefits of running simulations in such scenario.

Granted, the test on the board will run much faster than a simulation, but you are very much limited by the peripherals that are hooked up to the board. For example, how quickly can you run a new test after one has just completed? Also, there is the matter of synthesizing and implementing the design every time you want to run a new test after a code change.

Imagine how much quicker you can run simulations because you don’t have to go through the above steps. If one tests fails, you could be running another in the background while you debug the one that failed. And let’s not forget the debug capabilities that simulations provide. These include the ability to access internal registers in the design, compare waveforms, and much more.

For the rest of this article, visit the Aldec Design and Verification Blog.

SystemVerilog Functional Coverage in a Nutshell

 
March 15th, 2018 by Henry Chan

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that have occurred on your signals.

Consider an 8-bit address signal, paddr, and a 32-bit data signal, pwdata. Assigning a coverpoint to each signal will direct your simulator to track these signals during simulation and record the number of hits. For each coverpoint, bins can be created to organize the possible signal values into meaningful categories. Finally, a covergroup is used to encapsulate it all and is instantiated using the new() constructor. Associating the covergroup with a clock event is also a good way to trigger the coverage sampling.

Read the rest of SystemVerilog Functional Coverage in a Nutshell

How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1

 
February 28th, 2018 by Farhad Fallahlalehzari

When should we use the term “Vision for Everything”, as vision-based applications are entering various industries? It’s been a few years since the emergence of Embedded Vision and we see that it’s being used in a wide range of applications including Security, Medical, Smart homes, Robotics, Transportations, Automotive Driver Assistance Systems (ADAS) and Augmented Reality (AR).

This is the first in a series of blogs explaining what you need to know to start designing Embedded Vision applications which can be used in ADAS, from choosing the right device and tools to demystifying the vision algorithms used in automotive applications and how to implement them into FPGAs.

ADAS consists of two main parts, vision and sensor fusion. Cameras used in a smart car can provide the information such as object detection, classification and tracking. However, they don’t provide the distance between the vehicle and obstacles needed to prevent a collision. To do that, sensors such as LIDAR or RADAR come to play.

In this series of blogs, we will mainly focus on the vision side of the ADAS; but will cover sensor fusion in the future. The main goal of this series of blogs is to give an in-depth knowledge of Aldec’s complete ADAS reference design which includes 360-Degree Surrounding View, Driver Drowsiness Detection and Smart-Rear View.
Read the rest of How to develop an FPGA-based Embedded Vision application for ADAS, series of blogs – Part 1

Understanding the inner workings of UVM – Part 2

 
January 29th, 2018 by Vatsal Choksi

In this blog, my major focus is on explaining the concepts such as Sequence, Sequencer, Driver and showing how the communication takes place from sequence to sequencer and from sequencer to driver. In the previous blog, I included a top-level diagram of the UVM structure, showing different base classes. If you need refresh your memory on where the classes Sequence, Sequencer and Drivers stand please click https://www.aldec.com/en/company/blog/149–understanding-the-inner-workings-of-uvm.

So, let’s look at the main concepts and follow the communication mechanism they use for the effective execution of a test.
Read the rest of Understanding the inner workings of UVM – Part 2

How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA

 
January 25th, 2018 by Farhad Fallahlalehzari

A high-performance router is an absolute must if you want to run a high-traffic network in which different devices need to transfer and receive data as fast as possible. A router with a powerful processor and sufficient local memory reduces data hiccups and minimizes message loading and buffering times. But is that enough?

Because of the huge amount of data that people now generate – combined with the wealth of communication protocols, such as Wi-Fi, Ethernet, USB, SFP, QSFP – high-performance, hardware re-programmable routers are becoming popular. That hardware re-programmability is being delivered through FPGAs, and utilizing one as the main ‘processor’ on the router makes it easy to add or modify desired modules such as encryption and compression.

Read the rest of How to Design the New Generation of Reprogrammable Router/Switch Using Zynq FPGA

Partition your Design for FPGA Prototyping

 
December 11th, 2017 by Henry Chan

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM’s prototyping mode accounts for the limitations of the target FPGAs and allows the user to map a design to the FPGAs within these constraints.

Partitioning a design to fit into multiple FPGAs can be a lot of work

Designing the partitions with HES-DVM is as easy as selecting specific VHDL/SystemVerilog design modules from the hierarchy and moving them to a desired partition. All information about the design modules and the amount of LUTs, Flip-flops, memory blocks, DSP slices, and I/O consumed are displayed for convenience. These values can also be viewed as a percentage of the target FPGAs’ available resources allowing you to know when an FPGA is full.

Adding a module to a partition

Mapping a partition to an FPGA

Once the partitions are finalized, each partition can be assigned to a specific FPGA. A design successfully fitting into the FPGAs on the target prototyping board is only the beginning. There still remains a big problem with the sheer number of connections between the partitions. Modern designs have thousands of internal signals interconnecting major blocks or sub-systems. It’s likely that there won’t be a sufficient amount of direct connections between FPGAs to support the design’s internal wiring. How can the large amount of internal design signals possibly be accommodated by the relatively smaller amount of I/O available from the FPGAs?

For the rest of this article, visit the Aldec Design and Verification Blog.

Plots: A New Way To Analyze Data

 
November 29th, 2017 by Sunil Sahoo

Data analysis is often a very time consuming process for a hardware design or verification engineer. We always end up using the waveform viewer which may not be very efficient in giving us a high-level overview of what we’re looking for. Data that is spread across a long simulation cycle is very hard to visualize on the waveform. Whenever I have to analyze a huge chunk of data, I always wonder what would be the best way to do it. It is often cumbersome to go through even a millisecond’s worth of waveform data to analyze the bigger picture. There are of course other tools that can take a VCD file and perform an analysis but that involves buying and learning to use an additional tool.

Sometimes it’s not feasible to invest time and money into new tools. So we always go back to our trusty waveform viewer to make sense of the results. But what if there is a better way of analyzing such data, especially if you are doing some kind of signal processing application and have a lot of data that you would rather view in a format other than the time domain based representation of a waveform? For example, imagine you are trying to visualize the data of an FFT engine. On a waveform, it is next to impossible to visualize this.

In Riviera-PRO we have the Plots feature which can help you. The plot window ties directly to the simulation database, so you don’t have to code anything new or learn a new tool. Just with a few clicks you can add objects to the plot viewer and, based on the settings, it will generate a plot of that object. Sounds very simple but it gives you a bigger picture of what your design object is doing over the course of the entire simulation, rather than just the slice you can see on the waveform between two points of time.

For the rest of this article, visit the Aldec Design and Verification Blog.

Emulation in FPGA

 
November 22nd, 2017 by Krzysztof Szczur

For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather than capabilities they were called “Big Box” emulators and typically were used in order to recover some of the time lost on RTL simulation. Meanwhile, FPGA technology has been available long enough to mature to the point where FPGA based emulation became available – and I’m not talking here about FPGA prototyping.

“Emulation – Prototyping, aren’t they just synonyms?”

Sure, they are not. The most significant differences between FPGA usage in prototypes and in emulation are shown in table 1.

 

Prototyping

Emulation

Clock frequency

10-200 MHz

1-20 MHz

Clock Topology

Multiple asynchronous sources – limited number of domains

Derived from emulation core clock – unlimited number of domains

Speed Limitation

Fixed,
Determined by Inter-FPGA signal multiplexing

Adaptive,
Determined by FPGA-to-Host Comms, Inter-FPGA signal multiplexing

Stimulus Source

In-System, Real-world IO

Host,
Connection with simulators, virtual platforms, virtual models and other testbenches

Signal Capture

Selected Nodes

Full Visibility

Memory Models

Near-match to physical

Modelled

Design Setup

Computer aided but with extensive user’s input and decisions

Fully automated

Table 1: Typical differences between FPGA usage in prototyping and emulation

FPGAs are the fastest platform for prototyping, but we can also harness that speed into our verification environment, then we can achieve runtime performance 2x to 5x faster than traditional “big box” emulation systems, and all at a fraction of the cost per gate per MHz.

“FPGAs are way too small for our SoC design, aren’t they?”

In the HES-US-2640 board, Aldec already has the largest capacity single FPGA boards commercially available today. Connecting 4 such boards in a backplane gives you 24 largest Xilinx UltraScale chips in which you can implement 633 Million ASIC Gates and still have 40% of capacity margin to facilitate FPGA Place & Route.

Figure 1: Scalable HES platform for prototyping & emulation

Not all designs need such excessive capacity, especially IoT projects, where the primary requirement is small footprint and energy-safe design. You will find the proper configuration in Aldec HES boards versatile portfolio containing Virtex-7, Virtex UltraScale and Kintex UltraScale based hardware.

For the rest of this article, visit the Aldec Design and Verification Blog.

Code Coverage in HDL Editor? Now That’s a Nice Feature.

 
October 18th, 2017 by Sunil Sahoo

For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the ability to switch easily between the code and the coverage results. It is particularly helpful to have a way of navigating the hierarchy, selecting a coverage result and then being able to look into the source code and make changes.

I recently had occasion to explain to someone how the feature works in Aldec’s Riviera-PRO, and to reflect on the tool developments that led to this great capability. As you may be aware, Aldec has a number of legacy coverage tools that allow you to view the coverage results from within the simulator; and which give you easy access to the coverage results and the corresponding lines of code. With the introduction of our unified coverage database – in .acdb format – it became possible to see the code coverage results in a more flexible format. The biggest boost, in my opinion, was the introduction of a cross-probing capability.

For those of you who are wondering how to use this feature.

  • Open Riviera-PRO 2016.06 or newer and run your design with Coverage Enabled.
  • Open the datasets window (View-> Hierarchy and Objects-> Datasets).
  • Right-click in the window and select Add.
  • Add the .acdb file associated with your design (it should show up as Simulation n, where n is number).
  • Click on the newly added database.

For the rest of this article, visit the Aldec Design and Verification Blog.

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