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Posts Tagged ‘Embedded’

Not your Average UVM Testbench Generator – Unveiling at DAC 2019

Monday, May 20th, 2019

Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the internet until we held it in our hands and swiped to the next pages of seemingly infinite information. In the last decade, we saw how the automotive industry converted most of their mechanical systems into electronics and added Advanced Driving Assistance Systems (ADAS) for the safety of the passengers and other vehicles. We saw how home automation has transformed our daily life with the help of Automatic Speech Recognition (ASR) and low-power wireless technology.

The next decade ahead is even more exciting as new generation of SoCs will power new artificial intelligence (AI) applications that will touch human lives and transform various industries across the board.  For sure, the associated design and verification challenges and cost will only increase, and that’s why the EDA community has been preparing for it with the help of standards from Accellera such as UVM and now PSS.

As a company focused on design/verification of critical aspects of SoCs, we understand our place and know our role. Our goal is two-fold: automate verification and minimize functional flaws. At this year’s Design Automation Conference (DAC) in Las Vegas NV, we will showcase our most innovative solution yet that is built on top of our core code-generation technology. We call it Specta-AV™ – a massive UVM testbench generator that automates verification and minimizes functional flaws that originate from errors or changes in the spec.

UVM has been good and useful to us, and will continue to do so in the coming decade. But UVM is notorious for two main problems: its steep learning curve and the staggering amount of UVM code required to verify a full SoC. Verifying a custom IP with one master and slave agent requires tens of thousands of lines of UVM code. Verifying a full SoC requires multi-million lines of UVM code (in addition to the array of standard VIPs). Automating the process of creating UVM code is critical, and is a great solution to these two problems.

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Automating Register Verification with 100% Functional Coverage

Tuesday, December 4th, 2018

UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since Accellera’s release in 2011, UVM is now an IEEE standard published as IEEE 1800.2-2017 – IEEE Standard for Universal Verification Methodology Language Reference Manual.UVM has definitely gone a long way.

The UVM Register Layer classes have been quite useful for modeling memory-mapped registers and external memories in a DUT in which users are able to abstract the verification environment and standard tests from block to system level seamlessly with only minimum modifications. However, today’s average electronics consumer demand new use cases at ever-increasing speed and bandwidth – which certainly challenges SoC architects, designers and verification engineers, requiring them to be more creative in the implementation and modeling of the hardware/software interface (HSI). Modeling special registers is needed in order to meet special register behavior, which includes the popular types such as Shadow, Alias, Lock, Trigger-Buffer and Counter (only to name a few). Creating the RTL for these special registers may be easy to do for some experts but modeling them in UVM and manually creating the test environment with 100% functional coverage can be daunting.

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What ARE the Root Causes of Functional Flaws?

Thursday, November 1st, 2018

Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools.  The more the budget the better the resource they have for minimizing functional flaws.

I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.

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Agnisys at DVCon Europe

Tuesday, October 23rd, 2018

Our team is headed to Munich for DVCon Europe this week and we hope to see you there.

DVCon Europe- Booth #305
Munich, Germany
October 24-25, 2018

Related Press Release
Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface

Agnisys Inc., the leading EDA provider of the industry’s most comprehensive solution for Design and Verification of the Hardware/Software Interface (HSI), will present the latest release of IDesignSpec™ at DVCon Europe in Munich, Germany on October 24-25, 2018.

“The latest release of IDesignSpec includes several new features to address emerging challenges associated with HSI particularly for large SoC designs,” said Anupam Bakshi, CEO. “Our customers across the globe predominantly develop the newest and greatest SoCs in the market and their requirements continue to push our product capabilities towards unexplored territories – helping us innovate further.”

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The Current State of the Art of HSI – Live Webinar

Thursday, September 20th, 2018

UPDATE: This event has now passed.

If you missed it, please view the recorded version here: Hardware Software Interface (HSI) Specification and Productivity Improvement Recorded Webinar

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Join Agnisys for a free webinar on Thursday, September 27, 2018. I’ll be presenting as we take a deep dive into the current state of the art of HSI with a focus on the HSI layer in embedded systems.

The Hardware Software Interface is an integral part of any system development. Get this wrong and you can say adios to having a robust system. Get this right and say hello to productive teams and system development done right.

Register for a time that is convenient for you.

Hardware Software Interface (HSI) Specification and Productivity Improvement Webinar
Thursday, September 27, 2018
3:00 PM – 4:00 PM CEST OR 11:000 AM – 12:00 PM PDT

 




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