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Posts Tagged ‘FPGA’

Welcome Back to DAC – in Person – in San Francisco

Tuesday, November 30th, 2021

Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC). It’s the stimulating combination of a highly technical conference with peer-reviewed papers and a lively trade show with a large exhibit floor. DAC is one of the highlights of the year for many silicon and software vendors, especially those of us in the electronic design automation (EDA) space. Sure, it’s a lot of work and expense to participate in DAC, but there’s no substitute for it in my experience.

Last year, for the first time in its 57-year history, DAC was a virtual event. Of course, the pandemic has resulted in many of our activities taking place online rather than in person, and for the most part we’ve adapted surprisingly well. Unfortunately, I can’t say that about the virtual trade shows in which we’ve participated. Frankly, the exhibit portions of last year’s DAC and most other online shows have been disappointing in terms of attendance at our “booths” or the level of interaction we were able to have with our users and potential users.

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What ARE the Root Causes of Functional Flaws?

Thursday, November 1st, 2018

Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. For safety-critical systems such as the airplane engine control system, functional flaws can be catastrophic, and can lead to fatalities of all passengers. For both consumer-type and safety-critical systems, ASIC/FPGA teams strive to minimize functional flaws to the best of their abilities using their verification prowess with the help of EDA tools.  The more the budget the better the resource they have for minimizing functional flaws.

I just attended the webinar about the results of the Wilson Research Group & Mentor’s 2018 Functional Verification Study, and I can say that I’m not surprised with the results regarding root causes of functional flaws – this is what my team and I come across with frequently when we talk to our prospective customers and verification community.

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