Posts Tagged ‘SemiEDA’
Thursday, April 7th, 2022
Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system-on-chip (SoC) devices across a wide range of industries worldwide. We provide specification automation solutions for registers, sequences, testbenches, assertions, standard IP, block interconnection, documentation, and more. Every chip needs these elements, and every chip can benefit from our products. However, designs for certain applications have additional requirements that are also amenable to specification automation.
Safety-critical designs are a prominent example. There are many applications in which a chip failure could lead to catastrophic results. At a minimum, these designs should detect that something has gone wrong and take a safe course of action. If possible, they should continue to operate normally even after a fault occurs. This is especially important for applications such as satellites where repair or replacement of a failed component is difficult or impossible. It’s easy to think of cases in which safe operation in the presence of a fault is critical, including:
- Offensive and defensive weapons systems
- Vehicles for travel over road, track, air, and water
- Nuclear power plants
- Industrial applications where humans are at risk
- Implanted medical devices
For this post, I’d like to focus on road vehicles, especially automobiles. This is the safety-critical application with which everyday users have the most contact. Cars are a particularly challenging environment for electronics, with constant vibration and regular exposure to temperature and humidity extremes. Aging chips can fail, solder joints can break, cables can disconnect, alpha particles can flip memory bits—there’s no shortage of things that can go wrong. Accordingly, in 2011 the industry created a standard to guide the functionally safe design of electrical and electronic systems in road vehicles: ISO 26262.
Friday, December 31st, 2021
As we close in on the final days of 2021, I can’t help but think back over the events of the year and offer a few observations. At the front of my mind is the recent Design Automation Conference (DAC) in San Francisco. It was at an unusual time—December rather than June or July—and it was certainly not back to the full-scale show we all remember from the past. Some exhibitors pulled out due to pandemic-driven travel restrictions, and staffing at some booths was lower than usual. Nevertheless, it was still a very good show for Agnisys. It was great to see users in person again and to discuss their latest chip design and verification challenges.
It was also nice to be able to show them our latest tools and technologies, especially since we had a lot new to talk about. As I mentioned in my DAC preview post, we made two major announcements leading up to the show. The first was the release of IDS-FPGA, part of our IDesignSpec™ (IDS) family. IDS-FPGA is integrated with the Xilinx Vivado and Intel Quartus Prime software suites to make it easier to use our automated code and IP generators on FPGA projects. As we expected, we saw considerable interest in this new offering and enjoyed the chance to demonstrate it at our booth.
Tuesday, November 30th, 2021
Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC). It’s the stimulating combination of a highly technical conference with peer-reviewed papers and a lively trade show with a large exhibit floor. DAC is one of the highlights of the year for many silicon and software vendors, especially those of us in the electronic design automation (EDA) space. Sure, it’s a lot of work and expense to participate in DAC, but there’s no substitute for it in my experience.
Last year, for the first time in its 57-year history, DAC was a virtual event. Of course, the pandemic has resulted in many of our activities taking place online rather than in person, and for the most part we’ve adapted surprisingly well. Unfortunately, I can’t say that about the virtual trade shows in which we’ve participated. Frankly, the exhibit portions of last year’s DAC and most other online shows have been disappointing in terms of attendance at our “booths” or the level of interaction we were able to have with our users and potential users.
Monday, July 19th, 2021
In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property (IP) blocks and system-on-chip (SoC) designs. When we first started supporting register and memory automation, we focused on generating register-transfer-level (RTL) design descriptions and Universal Verification Methodology (UVM) simulation testbench models from executable specifications. You generate these outputs as soon as the specifications are ready and re-generate them every time that the specifications are updated throughout the project.
This is of clear benefit to design and verification engineers. The designers never have to write any RTL code for registers or memories, or update code manually when requirements change. Similarly, the verification team developing the UVM testbench for the IP or SoC incorporates the generated models without having to develop them by hand, and automatically updates them when needed. When we added sequence automation to our product family, we helped the UVM effort even more. Over time, we’ve added design and verification generation for a wide range of standards-based IP as well as SoC-level interconnection of IP and custom blocks.
Monday, May 31st, 2021
In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in system-on-chip (SoC) development since no team can afford to design and verify a billion or more gates from scratch. There’s no chance of this trend reversing, so we see a lot of interest in many types of design and verification IP, especially those that implement industry standards. We’ve been hard at work supporting users and expanding our IP titles, so I’d like to revisit the topic in this post.
It’s important to stress that we offer a library of IP generators, not fixed IP blocks. This is essential given the diversity of applications that use SoCs as well as the mix of technologies (FPGA, ASIC, and full custom) used to build these complex chips. Every chip project has its own requirements for its IP blocks, with a selection of features often arising from tradeoffs between speed, area, and power. Only a generation-driven solution can satisfy these needs. Options and customization must be built into the generators so that users are never tempted to manually edit register-transfer-level (RTL) design files.
Tuesday, April 27th, 2021
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced verification teams using more automated methods, the UVM brought everyone involved in chip development into a new era. Verification engineers have ready access to object-oriented programming, constrained-random stimulus, self-checking tests, reusable models, functional coverage, assertions, and more. Both the UVM itself and the SystemVerilog language upon which it is built are industry standards, allowing teams to mix EDA tools from multiple vendors, and easily switch tools if they wish.
Thursday, March 25th, 2021
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys User Group Educational Roundtable (AUGER) on March 18. We had a great event enhanced by lots of interaction with our users. Prior to that, we presented the paper “ML-Based Verification and Regression Automation” and the short workshop “RISC-V Based SoC Design, Verification and Validation in One Hour” at the annual Design and Verification Conference (DVCon) U.S. We also participated for the first time in DVClub Europe, where I discussed “Automating IP and SoC Verification.”
As part of preparing for these events, we took a step back and thought from the top down about the role we are playing in the industry today and the directions we can take in the future. We have expanded our original focus on register automation to encompass specification-driven design, verification, embedded programming, validation, and documentation of IPs and SoCs. This expansion is testament both to our growth as a company and to the many challenges faced by semiconductor development teams. Sheer complexity is the most obvious issue; today’s designs contain billions of gates with thousands of blocks and countless interconnections.
Friday, February 12th, 2021
In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s post I’d like to focus on a group even more vital to us than partners: the users themselves. I’m choosing this topic partly to highlight our very first Agnisys User Group Educational Roundtable (AUGER), coming up in a few weeks and held virtually as has become the norm for events in our current situation.
It seems axiomatic that users are important; if we don’t have customers using our products then we don’t have a business. But it goes deeper than that in EDA. As hard as we try to make our products easy to use, EDA tools have high support requirements. We rarely send a license off to a customer and never hear from them again until renewal time. The norm is that our applications engineering (AE) team builds a close relationship with users as they answer questions and provide guidance.
Monday, August 27th, 2018
As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a bit of tunnel vision as we busy ourselves with client meetings, conferences, socializing with potential new clients, and uncovering new ways to improve and expand ourselves globally.
My first official trip to Edinburgh snapped me out of that. Edinburgh, Scotland’s compact, hilly capital, is a magical place. From its medieval Old Town and elegant Georgian New Town with gardens, I couldn’t help but slow down and take the time to appreciate my surroundings.
As I slowed down, little details caught my eye. I marveled at the public transport – so connected, punctual, convenient, and cost-effective. Not to mention the jovial nature of the Scottish people and the greetings and smiles I received every morning from strangers.
Between meetings, I squeezed in a visit an ancient monument – the Edinburgh Castle, Scotland’s most-visited paid tourist attraction. The Scottish monuments were quite spectacular and intricately detailed.
It was interesting to read that at the time of second world war, the Crown Jewels were kept in the Castle under a toilet! Of course, I had to see them, they didn’t allow a picture of the original but here is a photo its brass replica.