Archive for the ‘Uncategorized’ Category
Monday, July 19th, 2021
In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property (IP) blocks and system-on-chip (SoC) designs. When we first started supporting register and memory automation, we focused on generating register-transfer-level (RTL) design descriptions and Universal Verification Methodology (UVM) simulation testbench models from executable specifications. You generate these outputs as soon as the specifications are ready and re-generate them every time that the specifications are updated throughout the project.
This is of clear benefit to design and verification engineers. The designers never have to write any RTL code for registers or memories, or update code manually when requirements change. Similarly, the verification team developing the UVM testbench for the IP or SoC incorporates the generated models without having to develop them by hand, and automatically updates them when needed. When we added sequence automation to our product family, we helped the UVM effort even more. Over time, we’ve added design and verification generation for a wide range of standards-based IP as well as SoC-level interconnection of IP and custom blocks.
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Tags: SemiEDA, SoC, SystemRDL, UVM
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Wednesday, June 23rd, 2021
If there’s one good thing to emerge amid all the challenges of the last year and a half, it’s improved technology for remote learning. On-line talks, webinars, and podcasts are nothing new, but with so many people working at home the importance of virtual options has grown. When was the last time you had a vendor physically visit your company in person to talk about a new tool or technology? When was the last time you attended an in-person conference or seminar? For many engineers, it has been well over a year since we were even in the office. We’ve relied on the web for just about everything.
At Agnisys, we’ve been doing regular webinars since well before the pandemic and they have been highly effective and successful. We offered a series last year that proved quite popular, and you may have noticed that we recently announced a new series that began a few weeks ago. With interest in remote learning at an all-time high, we fully expect a great turnout for all our upcoming virtual events. Even if you’ve attended some of our webinars before, I encourage you to check out our new series because we’re taking a dramatically different approach to the material.
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Tags: RTL, SoC, SystemRDL
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Monday, May 31st, 2021
In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in system-on-chip (SoC) development since no team can afford to design and verify a billion or more gates from scratch. There’s no chance of this trend reversing, so we see a lot of interest in many types of design and verification IP, especially those that implement industry standards. We’ve been hard at work supporting users and expanding our IP titles, so I’d like to revisit the topic in this post.
It’s important to stress that we offer a library of IP generators, not fixed IP blocks. This is essential given the diversity of applications that use SoCs as well as the mix of technologies (FPGA, ASIC, and full custom) used to build these complex chips. Every chip project has its own requirements for its IP blocks, with a selection of features often arising from tradeoffs between speed, area, and power. Only a generation-driven solution can satisfy these needs. Options and customization must be built into the generators so that users are never tempted to manually edit register-transfer-level (RTL) design files.
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Tags: RTL, SemiEDA
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Tuesday, April 27th, 2021
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced verification teams using more automated methods, the UVM brought everyone involved in chip development into a new era. Verification engineers have ready access to object-oriented programming, constrained-random stimulus, self-checking tests, reusable models, functional coverage, assertions, and more. Both the UVM itself and the SystemVerilog language upon which it is built are industry standards, allowing teams to mix EDA tools from multiple vendors, and easily switch tools if they wish.
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Tags: RTL, SemiEDA, SoC design, SystemRDL, UVM RAL
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Thursday, March 25th, 2021
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys User Group Educational Roundtable (AUGER) on March 18. We had a great event enhanced by lots of interaction with our users. Prior to that, we presented the paper “ML-Based Verification and Regression Automation” and the short workshop “RISC-V Based SoC Design, Verification and Validation in One Hour” at the annual Design and Verification Conference (DVCon) U.S. We also participated for the first time in DVClub Europe, where I discussed “Automating IP and SoC Verification.”
As part of preparing for these events, we took a step back and thought from the top down about the role we are playing in the industry today and the directions we can take in the future. We have expanded our original focus on register automation to encompass specification-driven design, verification, embedded programming, validation, and documentation of IPs and SoCs. This expansion is testament both to our growth as a company and to the many challenges faced by semiconductor development teams. Sheer complexity is the most obvious issue; today’s designs contain billions of gates with thousands of blocks and countless interconnections.
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Tags: SemiEDA, UVM
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Friday, February 12th, 2021
In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s post I’d like to focus on a group even more vital to us than partners: the users themselves. I’m choosing this topic partly to highlight our very first Agnisys User Group Educational Roundtable (AUGER), coming up in a few weeks and held virtually as has become the norm for events in our current situation.
It seems axiomatic that users are important; if we don’t have customers using our products then we don’t have a business. But it goes deeper than that in EDA. As hard as we try to make our products easy to use, EDA tools have high support requirements. We rarely send a license off to a customer and never hear from them again until renewal time. The norm is that our applications engineering (AE) team builds a close relationship with users as they answer questions and provide guidance.
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Tags: AUGER2021, SemiEDA
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Tuesday, January 26th, 2021
Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this topic, I asked myself whether this might be of interest to anyone beyond other EDA companies. After some consideration, I realized that who we partner with, and how, and why, is quite important for our users. In fact, when I talk with both prospective and current customers, this is a topic that comes up quite often. So, I decided to give some background on the way that EDA partnerships work and cite a few noteworthy examples.
Let me start with why the idea of partnerships exists at all. The reason is simple: users demand that their EDA vendors work together. The reality is that every chip development team uses tools from multiple vendors. No single vendor, not even any of the “Big 3” industry leaders, offers every possible tool and form of IP required for a comprehensive chip design and verification flow. Users need to be able to choose best-in-class tools from different vendors and deploy them together on a single project. However, users do not want to have to integrate and test the tools together all by themselves.
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Tags: EDA, SystemVerilog, testbench, UVM
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Friday, December 11th, 2020
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In fact, many argue that a chip must contain at least one embedded processor to qualify as an SoC. Embedded systems have many design and verification challenges, and these apply fully to SoCs. The silicon technology really doesn’t matter; embedded FPGA designs can be huge these days and every bit as complex as ASICs or full-custom chips. Tackling the development challenges for these systems requires an automated, unified flow that covers both hardware and software, spanning design, verification, software, and documentation.
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Tags: Agnisys, UVM
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Tuesday, November 17th, 2020
Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by embedded systems. Even adventurers exploring the most remote regions of our planet carry satellite phones for emergency contact. The ever-increasing role of electronics places huge demands for functional safety and security in the chips and systems we design. I’d like to explore these two topics a bit and recommend that you view a webinar that we recorded earlier this year for a deeper dive.
Let me start by differentiating the two terms, especially since “safety” and “security” tend to be used almost interchangeably in everyday speech. Functional safety has a specific meaning when applied to electronics and embedded systems: a measure of the system behaving correctly in response to a range of failures. One commonly cited example of such a failure is an alpha particle flipping a memory bit. If this occurs in safety-critical logic, the design must include a mechanism to detect the failure and correct it if possible. Other failure examples include human error, environmental stress, broken connections, and aging effects.
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Wednesday, October 28th, 2020
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation Conference (DAC). These innovations continue our history of building upon our expertise in the automation of register design and verification to encompass many other aspects of embedded systems development. We provide real value to your architects, designers, verification engineers, software developers, technical writers, and chip testers.
The key idea that links all our products and solutions is using an executable specification as the single source of information across all your project teams. From a single specification, you can generate design RTL, complex programming and test sequences, UVM testbench models for simulation, portable stimulus standard (PSS) models, assertions for formal verification, C code for firmware and device driver development, CSV files for automatic test equipment (ATE), and end-user documentation in multiple formats.
No duplication of information means no wasted time, money, or resources and no chance for multiple representations to get out of sync as the project evolves. Changes to the specification require only the push of a button to update all generated files. We support a wide range of specification formats, including industry standards such as IP-XACT and SystemRDL, popular tools such as Microsoft Word and Excel, and our own specialized editors. We generate output files in dozens of different formats to support the diverse users in your teams.
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