Archive for the ‘Registers’ Category
Thursday, January 11th, 2024
Specification automation means the automatic generation of RTL design, verification, software, validation, and documentation files from executable specifications. That’s what we enable with our solutions at Agnisys. Specification automation begins with register automation. I mean that historically: registers were the first aspect of design that we tackled, and we were true pioneers of this technology. But it’s still true today: nearly everyone who takes advantage of our specification automation solutions starts with registers.
Registers: The Fundamental Element
As discussed in a recent post, registers are some of the most common and fundamental design elements. Literally everyone on a chip or intellectual property (IP) project can benefit from register automation. Your designs may contain hundreds of thousands of registers, and designing these by hand is clearly a painful task. Just typing in the register-transfer-level or RTL design code requires weeks or months of work. Like any hard coding, it’s highly susceptible to human error. Especially with many similarly named registers, typos are certain to occur.
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Monday, May 20th, 2019
Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the internet until we held it in our hands and swiped to the next pages of seemingly infinite information. In the last decade, we saw how the automotive industry converted most of their mechanical systems into electronics and added Advanced Driving Assistance Systems (ADAS) for the safety of the passengers and other vehicles. We saw how home automation has transformed our daily life with the help of Automatic Speech Recognition (ASR) and low-power wireless technology.
The next decade ahead is even more exciting as new generation of SoCs will power new artificial intelligence (AI) applications that will touch human lives and transform various industries across the board. For sure, the associated design and verification challenges and cost will only increase, and that’s why the EDA community has been preparing for it with the help of standards from Accellera such as UVM and now PSS.
As a company focused on design/verification of critical aspects of SoCs, we understand our place and know our role. Our goal is two-fold: automate verification and minimize functional flaws. At this year’s Design Automation Conference (DAC) in Las Vegas NV, we will showcase our most innovative solution yet that is built on top of our core code-generation technology. We call it Specta-AV™ – a massive UVM testbench generator that automates verification and minimizes functional flaws that originate from errors or changes in the spec.
UVM has been good and useful to us, and will continue to do so in the coming decade. But UVM is notorious for two main problems: its steep learning curve and the staggering amount of UVM code required to verify a full SoC. Verifying a custom IP with one master and slave agent requires tens of thousands of lines of UVM code. Verifying a full SoC requires multi-million lines of UVM code (in addition to the array of standard VIPs). Automating the process of creating UVM code is critical, and is a great solution to these two problems.
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Tags: Agnisys, dac, Design and Verification, Embedded, Free register Generator, UVM, UVM registers
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Tuesday, February 19th, 2019
By Louie De Luna, Agnisys Director of Sales and Marketing
Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into mainstream technology. In EDA, the application of ML algorithms actually dates back to 2008 – when two Machine Learning-related topics were presented at DAC. The first topic, Efficient System Design Space Exploration Using Machine Learning Techniques targeted design challenges and the second, Experiences and Advances in Formal and Dynamic Verification, targeted verification challenges.
As a company focused on solving both design and verification challenges associated to Hardware/Software Interface (HSI), Agnisys has extensive experience in register code generation and verification, so applying Machine Learning to register automation is a natural next step for us. Agnisys register tool IDesignSpec is a fully-matured solution with a large user base, where it can generate register code directly from the specification in Word, Excel, IP-XACT or SystemRDL. But in an ideal world, our users would rather use plain and simple English text to describe the register behavior rather than use special properties and syntax. Natural, plain English is still the hallmark of specifications in today’s system design and a lot of useful and actionable information is embedded in the natural language specification text.
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Tags: Agnisys, Automation, DVCon, Free register Generator, functional verification, hsi, IDesignSpec, Register Generator
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Thursday, January 24th, 2019
Tools are made to automate a process, perform calculations, minimize errors and improve efficiencies, but at their core, tools are made to solve a given problem. Problems are found as a natural effect of progress. They come from the industry – in some cases from experts, innovators and tool vendors, and often times they come directly from the users or customers. As an EDA tool vendor, we serve highly-intelligent users who know their design and verification problems well as these have become roadblocks in their day to day work. But honestly these problems will not reach the tool vendor if there’s no mutual trust to begin with. I’m not referring to the routine support tickets that are filed, but to the technical problems that openly come up during face-to-face discussions. That’s our case with our portable sequence generator.
A few longtime users of our register generator tool shared with us their need to centralize the creation of sequences. The basic idea is to reuse the successful concept that we have in centralizing the creation of registers from a single spec – this concept has unified the IP, software, firmware, device driver and system integrator teams to work from a single source. Any changes to the register spec would typically only involve re-generation of the RTL, UVM regmodel, UVM testbench, C/C++ headers and documentation from the spec itself using built-in code generators. You don’t have to worry about which design and verification elements are impacted due to the register change, and you don’t have to manually modify a long list of register files to implement the change. Many of our users have found this concept and methodology valuable, so they have asked us to do the same thing for sequences.
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Tags: Design and Verification, ISequenceSpec, Register Generator, Specification, UVM, UVM registers, Verification
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Tuesday, December 4th, 2018
UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since Accellera’s release in 2011, UVM is now an IEEE standard published as IEEE 1800.2-2017 – IEEE Standard for Universal Verification Methodology Language Reference Manual.UVM has definitely gone a long way.
The UVM Register Layer classes have been quite useful for modeling memory-mapped registers and external memories in a DUT in which users are able to abstract the verification environment and standard tests from block to system level seamlessly with only minimum modifications. However, today’s average electronics consumer demand new use cases at ever-increasing speed and bandwidth – which certainly challenges SoC architects, designers and verification engineers, requiring them to be more creative in the implementation and modeling of the hardware/software interface (HSI). Modeling special registers is needed in order to meet special register behavior, which includes the popular types such as Shadow, Alias, Lock, Trigger-Buffer and Counter (only to name a few). Creating the RTL for these special registers may be easy to do for some experts but modeling them in UVM and manually creating the test environment with 100% functional coverage can be daunting.
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Tags: Embedded, Emulation, FPGA, Functional Verification, ISequenceSpec, Prototyping, SemiEDA, UVM, Verification
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Thursday, September 20th, 2018
UPDATE: This event has now passed.
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Join Agnisys for a free webinar on Thursday, September 27, 2018. I’ll be presenting as we take a deep dive into the current state of the art of HSI with a focus on the HSI layer in embedded systems.
The Hardware Software Interface is an integral part of any system development. Get this wrong and you can say adios to having a robust system. Get this right and say hello to productive teams and system development done right.
Register for a time that is convenient for you.
Tags: Embedded, hsi, IDS NextGen, Verification, webinar
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